Browsing by Author "Ko, Chih-Hsin"

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Cathodoluminescence studies of GaAs nano-wires grown on shallow-trench-patterned Si
(2010-11-19)
Lee, Ling
;
Fan, Wen-Chung
;
Ku, Jui-Tai
;
Chang, Wen-Hao
;
Chen, Wei-Kuo
The optical properties of GaAs nano-wires grown on shallow-trench-patterned Si(001) substrates were investigated by cathodoluminescence. The results showed that when the trench width ranges from 80 to 100 nm, the emission efficiency of GaAs can be enhanced and is stronger than that of a homogeneously grown epilayer. The suppression of non-radiative centers is attributed to the trapping of both threading dislocations and planar defects at the trench sidewalls. This approach demonstrates the feasibility of growing nano-scaled GaAs-based optoelectronic devices on Si substrates.
Cathodoluminescence studies of GaAs nano-wires grown on shallow-trench-patterned Si
(2010-11-19)
Lee, Ling
;
Fan, Wen-Chung
;
Ku, Jui-Tai
;
Chang, Wen-Hao
;
Chen, Wei-Kuo
The optical properties of GaAs nano-wires grown on shallow-trench-patterned Si(001) substrates were investigated by cathodoluminescence. The results showed that when the trench width ranges from 80 to 100 nm, the emission efficiency of GaAs can be enhanced and is stronger than that of a homogeneously grown epilayer. The suppression of non-radiative centers is attributed to the trapping of both threading dislocations and planar defects at the trench sidewalls. This approach demonstrates the feasibility of growing nano-scaled GaAs-based optoelectronic devices on Si substrates.
Characterizing the channel backscattering behavior in nanoscale strained complementary metal oxide semiconductor field-effect transistors
(2006-11-01)
Lin, Hono-Nien
;
Chen, Hung-Wei
;
Ko, Chih-Hsin
;
Ge, Chung-Hu
;
Lin, Horng-Chih
This work investigates the impact of different uniaxial strain polarities on channel backscattering in nanoscale complementary metal oxide semiconductor field-effect transistor (CMOSFET). Two carrier statistics, nondegenerate and degenerate-limited, are employed to extract the channel backscattering ratio, ballistic efficiency, and related backscattering factors. While the channel length scales down and the channel stress level increases further, the modulation of channel backscattering ratio, i.e., improved (degraded) by uniaxial tensile (compressive) strain, becomes more prominent. This observation holds true under both carrier statistics, which implies that the nondegenerate case with simple mathematics can be fairly used for evaluation. In addition, the correlation between strain-enhanced mobility gain and drain current improvement is found to be predicted well by the ballistic efficiency deduced with the nondegenerate carrier statistics.
Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs
(2006-08-01)
Lin, Hong-Nien
;
Chen, Hung-Wei
;
Ko, Chih-Hsin
;
Ge, Chung-Hu
;
Lin, Horng-Chih
The correlation between channel mobility gain (Delta mu), linear drain-current gain (AIdlin), and saturation draincurrent gain (Delta I-dsat) of nanoscale strained CMOSFETs are reported. From the plots of Delta I-dlin versus Delta I-dsat and ballistic efficiency (B-sat,B-PSS), the ratio of source/drain parasitic resistance (R-sat,R-PSS) to channel resistance (R-CH,R-PSS) of strained CMOSFETs can be extracted. By plotting Delta mu versus Delta I-dlin, the efficiency of Delta mu translated to Delta I-dlin is higher for strained pMOSFETs than strained nMOSFETs due to smaller R-SD,R-PSS-to-R-CH,R-PSS ratio of strained pMOSFETs. It suggests that to exploit strain benefits fully, the R-SD,R-PSS reduction for strained nMOSFETs is vital, while for strained pMOSFETs the Delta I-dli -to-Delta mu sensitivity is maintained until R-SD,R-PSS becomes comparable to/or higher than R-CH,R-PSS.
Experimental Demonstration of (111)-Oriented GaAs Metal-Oxide-Semiconductor Field-Effect-Transistors with Hetero-Epitaxial Ge Source/Drain
(2014)
Han, Tsung-Yu
;
Luo, Guang-Li
;
Cheng, Chao-Ching
;
Ko, Chih-Hsin
;
Wann, Clement H.
We demonstrate source/drain (S/D) design for GaAs n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) by embedding Ge into recessed S/D region to eliminate the intrinsic issues of the low solid solubility of dopants and low density of states (DOS) in GaAs material. For achieving high quality S/D epitaxy, the effects of substrate orientation and surface preparation on the quality of the epitaxial Ge film were investigated. High quality Ge film was successfully grown on the GaAs (111)A substrate by using a ultra high vacuum chemical vapor deposition (UHVCVD) tool and the significant improvement in the surface root-mean-square (RMS) roughness was observed as compared to that on the (100) substrate. The fabricated GaAs NMOSFET with hetero-Ge S/D exhibits an I-on/I-off ratio of similar to 2.5 x 10(2). Even though the performance can be further improved, we think our proposed scheme sheds the light on overcoming the issues of the low solid solubility of n-dopant and low DOS in III-V MOSFETs. (C) 2014 The Electrochemical Society. All rights reserved.
Ge Epitaxial Growth on GaAs Substrates for Application to Ge-Source/Drain GaAs MOSFETs
(2010)
Luo, Guang-Li
;
Han, Zong-You
;
Chien, Chao-Hsin
;
Ko, Chih-Hsin
;
Wann, Clement H.
Ge films were epitaxially grown on GaAs(100) substrates and Ga(0.88)In(0.12)As(100) virtual substrates using an ultrahigh vacuum/chemical vapor deposition system. The incubation time of Ge growth depends on Ga(In)As surfaces that were processed by different wet chemical solutions. Growth behaviors, such as island growth at the initial stages and selective growth into recessed regions of GaAs, were studied by transmission electron microscopy. To test the quality of Ge grown on GaAs, an n(+)-Ge/p-GaAs diode was fabricated. We propose that through Ge selective epitaxial growth, Ge can be used as the source-drain of a GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) to overcome some intrinsic limitations of this device. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3246000] All rights reserved.
III-V MOSFETs with a New Self-Aligned Contact
(2010)
Zhang, Xingui
;
Guo, Huaxin
;
Ko, Chih-Hsin
;
Wann, Clement H.
;
Cheng, Chao-Ching
We report the first demonstration of III-V n-MOSFETs with self-aligned contact technology. The self-aligned contact was formed using a salicide-like process which is compatible with CMOS process flow. A new epitaxy process was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. Nickel was deposited and annealed to form NiGeSi, and unreacted metal was removed. A second anneal diffuses Ge and Si into GaAs to form heavily n+ doped regions, and a novel self-aligned nickel germanosilicide (NiGeSi) ohmic contact was achieved. MOSFETs with the new self-aligned metallization process were realized.
Improvement of defect reduction in semi-polar GaN grown on shallow-trenched Si(001) substrate
(2012)
Lee, Ling
;
Chien, Kun-Feng
;
Chou, Wu-Ching
;
Ko, Chih-Hsin
;
Wu, Cheng-Hsien
The improved design of sub-micron trenches on Si(001) substrate was demonstrated for defect suppression in semi-polar selectively-grown GaN layers. Cathodoluminescence and transmission electron microscopy measurements revealed a dramatically decreased density of threading dislocations and stacking faults near the surface of the overgrown GaN layer when the trench width ranged from 500 to 1500 nm. It was observed that defects were effectively trapped inside the trench when the ratio of trench depth to the SiO2 thickness is less than 0.66. In addition, a significant reduction of intrinsic polarization electric field was achieved for the InGaN/GaN multiple quantum well on the GaN selectively grown from the Si trenches.
Nearly Dislocation-free Ge/Si Heterostructures by Using Nanoscale Epitaxial Growth Method
(2012-01-01)
Luo, Guang-Li
;
Ko, Chih-Hsin
;
Wann, Clement H.
;
Chung, Cheng-Ting
;
Han, Zong-You
The selective growth of germanium into nanoscale trenches on silicon substrates was investigated. These nanoscale trenches-the smallest size of which was 50 nm-were fabricated using the state-of-the-art shallow trench isolation technique. The quality of the Ge films was evaluated using transmission electron microscopy. It was found that the formation of threading dislocations (TDs) was effectively suppressed when using this deposition technique. It was considered that for the Ge grown in nanoscale Si areas (e. g., several tens of nanometers), the TDs were readily removed during cyclic thermal annealing, predominantly because their gliding distance to the SiO2 sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched Si substrates with a reduced defect density. (C) 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of Garry Lee
Optical Studies of GaAs Nanowires Grown on Trenched Si(001) Substrate by Cathodoluminescence
(2012-06-01)
Lee, Ling
;
Chien, Kun-Feng
;
Fan, Wen-Chung
;
Chou, Wu-Ching
;
Ko, Chih-Hsin
"The strains in GaAs nanowires, which were grown from 1700- to 80-nm-wide trenches on the Si(001) wafer with SiO2 masks, were investigated by cathodoluminescence. For 1700- to 500-nm-wide trenches, the in-plane tensile strain at 15 K decreases with the decreasing trench width. The strain increases abruptly when the trench width is 300 nm, and then decreases as the trench width is further decreased. The results revealed that the stress induced by the SiO2 sidewalls dominates when the width is less than the depth of the trench. This approach provides an effective technique to measure the strain of a single nanowire and helps for the demonstration of selectively-grown GaAs with a designed strain. (C) 2012 The Japan Society of Applied Physics"
Self-aligned contact metallization technology for III-V metal-oxide-semiconductor field effect transistors
(2011-05-01)
Zhang, Xingui
;
Guo, Huaxin
;
Lin, Hau-Yu
;
Cheng, Chao-Ching
;
Ko, Chih-Hsin
The demonstration of a salicidelike self-aligned contact technology for III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is reported. A thin and continuous crystalline germanium-silicon (GeSi) layer was selectively formed on n(+) doped gallium arsenide (GaAs) regions by epitaxy. A new self-aligned nickel germanosilicide (NiGeSi) Ohmic contact with good morphology was achieved using a two-step annealing process with precise conversion of the GeSi layer into NiGeSi. NiGeSi contact with the contact resistivity (rho(c)) of 1.57 Omega mm and sheet resistance (R(sh)) of 2.8 Omega/square was achieved. The NiGeSi-based self-aligned contact technology is promising for future integration in high performance III-V MOSFETs. (C) 2011 American Vacuum Society. [DOI: 10.1116/1.3592211]
Strain-induced channel backscattering modulation in nanoscale CMOSFETs
(2006)
Chen, Hung-Wei
;
Lin, Hong-Nien
;
Ko, Chih-Hsin
;
Ge, Chung-Hu
;
Lin, Horng-Chih
The channel backscattering ratios as well as the ballistic efficiency of strained CMOSFETs were studied for both nondegenerate and degenerate-limited cases. We found that the simple nondegenerate assumption can predict strain-induced change of ballistic efficiency with fair accuracy. The mechanism of drain current dependence on strain-induced mobility change was also investigated based on channel backscattering theory.
The Annihilation of Threading Dislocations in the Germanium Epitaxially Grown within the Silicon Nanoscale Trenches
(2009)
Luo, Guang-Li
;
Huang, Shih-Chiang
;
Ko, Chih-Hsin
;
Wann, Clement H.
;
Chung, Cheng-Ting
We investigated the selective growth of germanium into nanoscale trenches on silicon substrates. These nanoscale trenches, the smallest size of which was 50 nm, were fabricated using the state-of-the-art shallow trench isolation technique. The quality of the Ge films was evaluated using transmission electron microscopy. The formation of threading dislocations (TDs) was effectively suppressed when using this deposition technique. For the Ge grown in nanoscale Si areas (e.g., several tens of nanometers), the TDs were probably readily removed during cyclic thermal annealing predominantly because their gliding distance to the SiO(2) sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched Si substrates with a reduced defect density.