Browsing by Author "Kuo, Po-Yi"

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Back-Channel Etched Double Layer In-W-O/In-W-Zn-O Thin-Film Transistors
(2018-01-01)
Li, Zhen-Hao
;
Kuo, Po-Yi
;
Chen, Wen-Tzu
;
Liu, Po-Tsun
;
光電工程學系
The thin-film transistors (TFTs) with back-channel etched (BCE) type enable channel length to be narrow and reduce parasitic capacitances owing to its shorter overlaps between the gate and source/drain (S/D) electrodes. In this study, a high-performance BCE-type oxide thin-film transistor was proposed for investigation. A novel stacked double layer In-W-O (IWO) / In-W-Zn-O (IWZO) channel structure was fabricated and developed. Respectively, IWZO exhibits a high resistance to back-channel etching damage and IWO channel achieve a high mobility. The double layer IWO/IWZO TFTs are promising candidates for driving active matrix organic light-emitting diode (AMOLED) and high resolution display applications in the future. The double layer IWO/IWZO TFTs with S/D pattern by H2O2 + KOH can exhibit the high-performance electrical characteristic. The field-effect mobility (mu FE) similar to 21.1cm(2)/V-s, subthreshold swing (S.S.) similar to 0.15 V/dec., threshold voltage (V-TH) similar to -0.092 V, and on/off ratio similar to 4.88x10(8) can be achieved.
Characteristics of self-aligned Si/Ge T-gate poly-Si thin-film transistors with high ON/OFF current ratio
(2007-05-01)
Kuo, Po-Yi
;
Chao, Tien-Sheng
;
Hsieh, Pei-Shan
;
Lei, Tan-Fu
;
電子物理學系
In this paper, we have successfully developed and fabricated self-aligned Si/Ge T-gate poly-Si thin-film transistors (Si/Ge T-gate TFTs) with a thick gate oxide at the gate edges near the source and drain for the first time. The Si/Ge T-gate was formed by selective wet etching of Ge gate layer. The thick gate oxide layer at the gate edges and passivation oxide layer were deposited simultaneously in passivation process. The thick gate oxide at the gate edges effectively reduces the drain vertical and lateral electric fields without additional mask, lightly doped drain, spacer, or subgate bias. The Si/Ge T-gate TFTs not only,reduce the OFF-state leakage current but also maintain a high ON-state current. Experimental results show that the Si/Ge T-gate TFTs have low OFF-state leakage currents, improved ON/OFF current ratio, and more saturated output characteristics compared with conventional TFTs.
Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals
(2010-08-01)
Chiang, Tsung-Yu
;
Wu, Yi-Hong
;
Ma, William Cheng-Yu
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Kuo, Po-Yi
;
Wang, Kuan-Ti
In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V(g) = 6 V, V(d) = 7 V and V(g) = -7 V, V(d) = 10 V, respectively), greater tolerable gate and drain disturbance (V(t) shift < 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 mu s with a 2-V shift of V(t) under V(g) = V(d) = 6 V operation), good retention time (> 10(8) s for 13% charge loss), and excellent endurance performance (after 10(4) P/E cycles with a memory window of 3 V).
Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs
(2017-07-01)
Hsieh, Dong-Ru
;
Lin, Jer-Yi
;
Kuo, Po-Yi
;
Chao, Tien-Sheng
;
電子物理學系
In this paper, the electrical characteristics of the Pi-gate junctionless FETs (PG JL FETs) with the in situ n(+) doped poly-Si (DP-Si) fin-channels have been experimentally investigated and comprehensively discussed. The subthreshold behavior and threshold voltage of the PG JL FETs are sensitive to the channel dimensions, especially the channel width. The crystallinity, carrier mobility, and effective carrier concentration in the DP-Si films are dependent on the initial DP-Si film thicknesses, which directly influence the on current and threshold voltage of the PG JL FETs. Based on an evaluation on the subthreshold behavior and the driving current, we found that the PG JL FETs with the low/high aspect ratio (A.R. = channel thickness/channel width) are separately suitable for the low-power/high-performance applications. Among these PG JL FETs, the device with a proper A.R. (3.35) exhibits a relatively steep subthreshold swing (S.S.) of 66 mV/decade and the highest (ON)/(OFF) currents ratio (I-ON/I-OFF) of 1.2 x 10(8) (VD = 1 V). These devices are very promising candidates for future multifunctional 3-D integrated circuit applications.
Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack
(2018-08-30)
Ruan, Dun-Bao
;
Liu, Po-Tsun
;
Chiu, Yu-Chuan
;
Kuo, Po-Yi
;
Yu, Min-Chin
The amorphous indium gallium zinc oxide thin-film transistors (TFTs) with a multilayer high-k gate stack are investigated in this research. In order to achieve a high quality gate insulator for plastic flexible display application, the multilayer high-k gate stacks (SiO2/TiO2/HfO2) are deposited by a low-temperature physical vapor deposition (PVD) process. On the other hands, an interfacial layer between the high-k stack and metal oxide channel is important for the device performance. The effects of interfacial layer material (SiO2 or Ga2O3) are also discussed in this report. The devices with SiO2 interfacial layer show a high on/off current ratio of similar to 7x10(7) for its low gate leakage current, a small sub-threshold swing of 0.093 V/decade and a high field-effect mobility of similar to 37.8 cm(2)/Vs for its good interface condition and low interface defeats. This research shows that the interface engineering of multilayer PVD gate stacks is necessary for oxide TFT fabrication.
Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs
(2020-02-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
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Kuo, Po-Yi
;
Chung, Chun-Chih
In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors with a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because of the difference in size and curvature between planar and TG or GAA structures. Because of the addition of an underlying ZrO2 seed layer, Hf ZrxO2 in the gate-stack has been crystallized before the PMA process. In addition, two different gate-stack configurations, MFM-insulator-semiconductor (MFMIS) and metal-FE-insulator-semiconductor (MFIS), were investigated for the GAA structure. We determined that MFMIS displayed considerably more favorable subthreshold behavior and ON-state current compared with MFIS. NC-related phenomena, such as negative drain-induced barrier lowering and negative differential resistance, were observed.
Effects of Backchannel Passivation on Electrical Behavior of Hetero-Stacked a-IWO/IGZO Thin Film Transistors
(2018-01-01)
Liu, Po-Tsun
;
Chang, Chih-Hsiang
;
Kuo, Po-Yi
;
Chen, Po-Wen
;
光電工程學系
This study investigates the effects of positive gate-bias stress (PGBS) on the electrical instability of amorphous InWO/InGaZnO (a-IWO/IGZO) stacked thin-film transistors (TFTs) with a backchannel passivation layer of SiO2 or Al2O3 film. After the application of PGBS to a-IWO/IGZO TFTs with an SiO2 passivation layer, abnormal negative threshold voltage (Vth) shifts were observed, while positive Vth shifts were observed in the TFTs with an Al2O3 passivation layer. This unusual positive bias instability is explained using a two-step electrical degradation behavior model, including both electron trapping and moisture absorption at the damaged back channel interface between a-IWO/IGZO TFTs and the SiO2 passivation layer. (C) 2018 The Electrochemical Society.
Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process
(2019-01-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
;
Kuo, Po-Yi
;
Chung, Chun-Chih
We have experimentally demonstrated fully suspended nanowire ( NW) gate-all-around (GAA) negative-capacitance (NC) field-effect transistors (FETs) with ultrasmall channel dimensions (5-nm x 12.5-nm); they exhibit a remarkable I-on-I-off ratio of over 10(10). This work, for the first time, experimentally studies and compares the structures of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NCFETs. The GAA with the MFMIS structure has a higher on-state current owing to the metallic equal-potential layer and superior S.S.(min) of 39.22 mV/decade. A ZrO2 seed-layer is inserted under Hf Zr1-x O-x (HZO) to improve the ferroelectric crystallinity. Consequently, post-metal annealing (PMA), the conventional crystallization annealing step, can be omitted in the presence of o-phase. The gate current (I-G) is monitored to verify the multi-domain HZO. A negative DIBL of -160 mV/V is observed because of the strong NC effect corresponding to previous simulated results.
Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
(2019-11-01)
Lee, Shen-Yang
;
Chen, Han-Wei
;
Shen, Chiuan-Huei
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Kuo, Po-Yi
;
Chung, Chun-Chih
For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of $5.3\times9$ nm(2) and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable I-on-I-off ratio of more than 10(8). We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage ( ${V}_{\textit {TH}}$ ) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub- ${V}_{\textit {TH}}$ slope of 43.85 and 26.84 mV/dec, respectively. An additional ZrO2 seed layer was inserted under the Hf $_{{1-}{x}}$ ZrxO2 layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase ( ${o}$ -phase) before further post-metal annealing (PMA).
Fabrication and Characterization of Pi-Gate Poly-Si Junctionless and Inversion Mode Fin-FETs for 3-D IC Applications
(2016)
Hsieh, Don-Ru
;
Lin, Jer-Yi
;
Kuo, Po-Yi
;
Chao, Tien-Sheng
;
電子物理學系
In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) Fin-FETs have been successfully fabricated and demonstrated without using costly lithography technique. The PG JL Fin-FETs show excellent electrical performance in terms of low gate overdrive voltage, extremely near-ideal subthreshold swing (S.S.) similar to 68 mV/dec., steep average subthreshold swing (A.S.S.) similar to 73 mV/dec., smaller drain induced barrier lowing (DIBL) similar to 9 mV/V, and higher I-on/I-off ratio similar to 1.1 x 10(8) (V-D = 1 V).
High Mobility Tungsten-Doped Thin-Film Transistor on Polyimide Substrate with Low Temperature Process
(2018-01-01)
Ruan, Dun-Bao
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Liu, Po-Tsun
;
Chiu, Yu-Chuan
;
Yu, Min-Chin
;
Gan, Kai-jhih
A novel high mobility channel material, amorphous tungsten doped indium-oxide, is used as the active layer of flexible TFT, which is fabricated on a transparent polyimide under a low temperature process. The effects of channel thickness are investigated as well in this work. The flexible TFT with a suitable thickness of IWO film shows a high carrier mobility and low sub-threshold swing. The improvement can be attributed to increased donor-like oxygen vacancy with the thickness of channel layer increased.
High Performance Amorphous In-W-Zn-O Thin Film Transistor with Ultra-Thin Active Channel for Low Voltage Operation
(2018-01-01)
Liu, Po-Tsun
;
Kuo, Po-Yi
;
Hsu, Shan-Ming
;
光電工程學系
;
光電工程研究所
Amorphous indium tungsten zinc oxide (a-IWZO) ultra-thin film TFTs (UTFTs) have been successfully fabricated and demonstrated in this work. Tungsten oxide (WO3)-doped indium zinc oxide was developed because WO3 doping can form stable semiconducting films with various carrier mobilities and carrier concentration. The novel IWZO UTFTs with high-kappa HfO2 gate insulator exhibit superior potential for the power-saving applications of flat panel displays (FPDs), flexible electronics, and large scale integration (LSI) technologies owing to its outstanding characteristics of low threshold voltage similar to -0.072 V, high field-effect mobility (mu(FE)) similar to 23.8 cm(2)/V-s, excellent subthreshold swing similar to 72.6 mV/dec., low voltage operation (low power consumption), high electrical reliability, and small hysteresis.
High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n(+)-Doped Poly-Si NWs Channels Junctionless FETs
(2014-11-01)
Kuo, Po-Yi
;
Lu, Yi-Hsien
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
The gate-all-around sidewall-damascened sub-10- nm in situ n(+)-doped poly-Si nanowires channels junctionless FETs (GAA SWDNW-JLFETs) with one NW of sub-50-nm(2) cross-sectional area have been successfully fabricated and demonstrated in the category of poly-Si NWs JL transistors for the first time. Some key properties are explored: 1) novel SWDNW processes; 2) dependence of threshold voltage (V-TH) and subthreshold swing (S.S.) on dimension of in situ n(+)-doped poly-Si NWs in GAA SWDNW-JLFETs; and 3) thermal stability of main electrical characteristics under high operating temperature. The high-performance GAA SWDNW-JLFETs show good electrical characteristics: 1) steep S.S. similar to 75 mV/decade; 2) low gate supply voltage (V-G) = 1.5 V; 3) high ON/OFF currents ratio (I-ON/I-OFF) similar to 8 x 10(7) and significantly highthermal stability without implantation processes and hydrogenrelated plasma treatments for future 3-D integrated circuits, system-on-panel, and system-on-chip applications.
High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET
(2016-11)
Hsieh, Dong-Ru
;
Lin, Jer-Yi
;
Kuo, Po-Yi
;
Chao, Tien-Sheng
;
電子物理學系
In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width similar to 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shape of channels can be controlled effectively by rectangular silicon nitride (Si3N4) as hard masks; 3) the series resistance can be reduced by raised source/drain configurations; and 4) Si-compatible low thermal budget process. The PG polySi JL FETs show excellent electrical performance in terms of low gate overdrive voltage (V-G-V-TH = 2 V), extremely nearideal subthreshold swing (S.S.) similar to 68 mV/decade, steep average subthreshold swing (A.S.S.) similar to 73 mV/decade, smaller drain-induced barrier lowering similar to 9 mV/V, a higher ON/OFF current ratio similar to 1.1 x 10(8) (VD = 1 V), and a better field-effect mobility (mu(FE)) similar to 35 (cm(2)/Vs) as compared with PG poly-Si IM FETs. Thus, these devices are very promising for future 3-D integrated circuits applications.
High-Performance Poly-Si TFTs of Top-Gate with High-kappa Metal-Gate Combine the Laser Annealed Channel and Glass Substrate
(2011)
Lu, Yi-Hsien
;
Chien, Chao-Hsin
;
Kuo, Po-Yi
;
Yang, Ming-Jui
;
Lin, Hsiao-Yi
We demonstrate high-performance low-temperature poly-Si thin film transistors (LTPS-TFTs) with a TaN/Hf-based top-gate-stack and combine the channel film by laser annealing and glass substrate (glass substrate high-kappa metal-gate thin film transistor, called GSHM-TFTs). The GSHM-TFTs of n-channel (called GSHM-NTFTs) exhibit a very low threshold voltage, low supply voltage (similar to 2 V), steep subthreshold swing (S.S.) similar to 95 mV/dec, and high I(ON)/I(OFF) ratio >10(7). In contrast, GSHM-TFTs of p-channel (called GSHM-PTFTs) exhibit an S.S. similar to 154 mV/dec and an I(ON)/I(OFF) ratio even higher than 10(8). Furthermore, the driving currents are also enhanced in GSHM-TFTs. These significant improvements are due to the combination of laser annealed channel film and the very high gate-capacitance density provided by HfO(2) gate dielectrics with the effective oxide thickness of 14 nm. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3504147] All rights reserved.
High-Performance Poly-Si Thin-Film Transistors With L-Fin Channels
(2012-02-01)
Lu, Yi-Hsien
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Kuo, Po-Yi
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Lin, Je-Wei
;
Wu, Yi-Hong
;
Chen, Yi-Hsuan
For the first time, we construct poly-Si thin-film transistors (TFTs) with novel L-shaped poly-Si fin channels (poly-Si TFTs with L-fin channels, called LFin-TFTs). The L-fin channels of LFin-TFTs are similar to the multiple-gated fin channels of FinFETs. The LFin-TFTs exhibit a low supply gate voltage (3 V), a good subthreshold swing (SS) similar to 190 mV/dec, and a high on/off current ratio (I-ON/I-OFF) > 10(6) (V-D = 1 V) without hydrogen-related plasma treatments. After Ni salicidation, the devices exhibit steep SS similar to 148 mV/dec and I-ON/I-OFF similar to 10(7). After NH3 plasma treatment, the characteristics of the devices are further improved. The LFin-TFTs have steeper SS similar to 132 mV/dec, higher I-ON/I-OFF > 10(7), and threshold voltage (V-TH) similar to 0.036 V.
High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique
(2017-02)
Hsieh, Dong-Ru
;
Kuo, Po-Yi
;
Lin, Jer-Yi
;
Chen, Yi-Hsuan
;
Chang, Tien-Shun
In this paper, strained channel-sidewall damascened tri-gate polycrystalline silicon thin-film transistors (SC-SWDTG TFTs) have been successfully fabricated and then demonstrated by an innovative process flow. This process flow without the use of advanced lithography processes combines the sidewall damascened technique (SWDT) and two strain techniques, namely, the strain proximity free technique (SPFT), and the stress memorization technique (SMT), in the poly-Si channels. It has some advantages: (1) the channel shapes and dimensions can be effectively controlled by the wet etching processes and the deposition thickness of the tetraethoxysilane (TEOS) oxide; (2) the source/drain (S/D) resistance can be significantly decreased by the formation of the raised S/D structures; (3) the SPFT, SMT, and the rapid thermal annealing (RTA) treatment can enhance the performance of the SC-SWDTG TFTs without the limitation of the highly scaling stress liner thickness in deep-submicron TFTs. Thus, the SC-SWDTG TFTs exhibit a steep subthreshold swing (S.S.) similar to 110mV/dec., an extremely small drain induced barrier lowing (DIBL) similar to 12.2mVV(-1), and a high on/off ratio similar to 10(7) (V-D = 1V) without plasma treatments for future three-dimensional integrated circuits (3D ICs) applications.
Implantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionless FETs with Sub-1V Gate Operation and Near Ideal Subthreshold Swing
(2015)
Kuo, Po-Yi
;
Lin, Jer-Yi
;
Chao, Tien-Sheng
;
電子物理學系
;
Department of Electrophysics
The implantation free gate-all-around (GAA) double spacer poly-Si nanowires (NWs) channel junctionless (JL) FETs (GAA DS-NW JL-FETs) have been successfully fabricated and demonstrated in the category of poly-Si NW FETs for the first time. We have scaled down the NW dimension (D-NW) - length (L-NW) x width (W-NW) x thickness (T-NW) - to 80nmx13nmx3nm by novel double spacer NW (DS-NW) processes without use of electron beam (e-beam) lithography tools. GAA DS-NW JL-FETs show good electrical characteristics: near ideal subthreshold swing (S.S.) similar to 61mV/dec., steep driving swing (D.S.) similar to 82mV/dec., and sub-1V gate operation without implantation processes for future three-dimensional integrated circuits (3-D ICs), system-on-panel (SOP) applications.
Investigation of Channel Doping Concentration and Reverse Boron Penetration on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode FETs
(2018-01-01)
Hsieh, Dong-Ru
;
Chan, Yi-De
;
Kuo, Po-Yi
;
Chao, Tien-Sheng
;
電子物理學系
In this paper, the influence of channel doping concentration and reverse boron penetration on p-type Pi-gate (PG) poly-Si junctionless accumulation mode (JAM) FETs has been experimentally investigated and discussed. Effective carrier concentration (N-eff) and threshold voltage (V-TH) are found to be sensitive to doping concentration. Moreover, the positive shift in V-TH and the degradation in the subthreshold behavior for PG JAM FETs are observed after an additional source/drain (S/D) activation process. Using a low thermal-budget S/D activation process, PG JAM FETs with a suitable channel doping concentration can show excellent electrical characteristics: 1) steep subthreshold swing of 86 mV/dec.; 2) low average subthreshold swing (A.S.S.) of 96 mV/dec.; and 3) high ON/OFF current ratio (I-ON/I-OFF) of 7.7 x 10(7) (I-ON at V-G - V-TH = -2 V and V-D = -1 V).
Investigation of low operation voltage InZnSnO thin-film transistors with different high-k gate dielectric by physical vapor deposition
(2018-08-30)
Ruan, Dun-Bao
;
Liu, Po-Tsun
;
Chiu, Yu-Chuan
;
Kan, Kai-Zhi
;
Yu, Min-Chin
Amorphous Indium-Zinc-Tin-Oxide thin-film transistors (a-IZTO TFT) using different types of high-k materials (like HfO2, ZrO2 and Al2O3) as gate dielectric are studied in this work. All gate dielectric films were deposited by physical vapor deposition (PVD) process for better composition control. Compared with the traditional SiO2 gate insulator, a high-k gate dielectric can reduce the operation voltage of TFT device significantly. The TFT device with ZrO2 gate insulator exhibits a small subthreshold swing of 0.126 V/decade, high field-effect mobility of similar to 40.7 cm(2)/Vs, low threshold voltage of -0.05 V, and large On/Off current ratio of similar to 1.01 x 10(7). The mechanisms for electrical improvements are also investigated. These results demonstrate the potential application of PVD-deposited ZrO2 thin film as a promising gate dielectric in oxide-based thin-film transistors.