Browsing by Author "LEE, CY"

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A new multi-path tree-search FSVQ architecture for image/video sequence coding
(1995)
CHAO, YJ
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LEE, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
(1992-03-01)
WU, CY
;
KER, MD
;
LEE, CY
;
KO, J
;
電控工程研究所
A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800-mu-m2, the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than +/- 1 and +/- 10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCR's can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies.
A PARALLEL BIT-LEVEL MAXIMUM MINIMUM SELECTOR TO DIGITAL AND VIDEO SIGNAL-PROCESSING
(1994-10-01)
LEE, CY
;
JUAN, SC
;
YANG, WW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel circuit for parallel bit-level maximum/minimum selection. The selection is based on a label-updating scheme which sequentially scans a set of data patterns from MSB to LSB and generates corresponding labels. The complete circuit realizing this scheme consists of a set of updating units and a global OR unit, where each updating unit is composed of only a few basic gates. Due to structure modularity, the developed circuit provides a very cost-effective hardware solution for comparing large volumes of data patterns as those required in digital and video signal processing.
AN AREA-EFFICIENT MEDIAN FILTERING IC FOR IMAGE VIDEO APPLICATIONS
(1993-08-01)
HSIEH, PW
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TSAI, JM
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LEE, CY
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電控工程研究所
;
Institute of Electrical and Control Engineering
An area efficient IC for high-throughput median filtering applications is presented in this paper. This IC implements a modified delete-and-insert sorting algorithm which is very efficient for running order statistics applications. In hardware design, we first map the algorithm onto a regular PE structure, where each PE consistis of shift register, comparator, and some control gates. Then we conduct full-custom circuit/layout design of the PE to meet performance requirement. A proto-type chip for 64 input samples is implemented and tested. Results show that clock rate up to 50 MHz can be achieved using a 1.2 mum CMOS double metal technology. Two outstanding features of this IC are: (1) any specified order of input patterns can be produced within one clock cycle; (2) each chip can handle at most 64 data and can be cascaded as the number of sorted data is over 64. Thus this IC releases the bottle-neck of median search in hardware realization for many system designs, making real-time performance achievable.
An efficient memory architecture for motion estimation processor design
(1995)
TZENG, EG
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LEE, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
AN ON-CHIP ESD PROTECTION CIRCUIT WITH COMPLEMENTARY SCR STRUCTURES FOR SUBMICRON CMOS ICS
(1994)
KER, MD
;
WU, CY
;
JIANG, HC
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LEE, CY
;
KO, J
DESIGN OF A FAST SEQUENTIAL DECODING ALGORITHM BASED ON DYNAMIC SEARCHING STRATEGY
(1994)
YANG, WW
;
JENG, LF
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LEE, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
DIFLUOROSILYLENE AS A PRECURSOR FOR THE CHEMICAL VAPOR-DEPOSITION OF TITANIUM SILICIDE
(1992-09-01)
CHEN, CC
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YU, JL
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LEE, CY
;
LIU, CS
;
CHIU, HT
A new method for preparing thin films of titanium silicide, TiSi2, by chemical vapour deposition of difluorosilylene and titanium tetrachloride is reported.
EFFECT OF SIH4/CH4 FLOW RATIO ON THE GROWTH OF BETA-SIC ON SI BY ELECTRON-CYCLOTRON-RESONANCE CHEMICAL-VAPOR-DEPOSITION AT 500-DEGREES-C
(1995-01-09)
LIU, CC
;
LEE, CY
;
CHENG, KL
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CHENG, HC
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YEW, TR
FAST SEQUENTIAL-DECODING ALGORITHM-BASED ON DYNAMIC SEARCHING STRATEGY
(1994-10-01)
LEE, CY
;
YANG, WW
;
JENG, LF
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交大名義發表
;
電子工程學系及電子研究所
The authors present a new sequential decoding algorithm based on dynamic searching strategy to improve decoding efficiency. The searching strategy is to exploit both 'sorting' and 'path recording' techniques. By means of sorting, it is possible to identify the correct path in a very fast way and then, by the recording, the bit sequence can be recovered without degrading decoding performance. The authors also develop a conditional resetting scheme to overcome the buffer overflow problem encountered in conventional sequential decoding algorithms. Simulation results show that, for a given code, the decoding efficiency remains the same as that obtained from maximum likelihood function by appropriately selecting sorting length and decoding depth. In addition, this algorithm can easily be mapped onto an area-efficient VLSI architecture to implement long constraint length convolutional decoders for high-speed digital communications.
FINITE STATE VECTOR QUANTIZATION WITH MULTI-PATH TREE SEARCH STRATEGY FOR IMAGE VIDEO CODING
(1994)
JUAN, SC
;
CHAO, YJ
;
LEE, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
HIGH-SPEED MEDIAN FILTER DESIGNS USING SHIFTABLE CONTENT-ADDRESSABLE MEMORY
(1994-12-01)
LEE, CY
;
HSIEH, PW
;
TSAI, JM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a very efficient VLSI architecture for real-time median filtering as requested in many image/video applications, The median is obtained by first sorting input sequences and then selecting identified order according to the number of inputs, To reach the goal of high-speed data sorting, an optimized delete-and-insert algorithm is derived and then mapped onto shiftable content-addressable memory architecture, The complete design can be decomposed into a set of processor elements, where each processor element consists of two basic cells- sort-cell and compare-cell, Thus the design becomes very regular, More specifically any specified order can be obtained within one cycle and a high-speed clock rate can be achieved, A proto-type chip for 64 samples based on this architecture has been implemented and tested, Results show that a clock rate up to 50 MHz can be achieved using a 1.2 mu m CMOS double metal technology.
HIGH-THROUGHPUT DATA COMPRESSOR DESIGNS USING CONTENT ADDRESSABLE MEMORY
(1994)
YANG, RY
;
LEE, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
HIGH-THROUGHPUT DATA COMPRESSOR DESIGNS USING CONTENT-ADDRESSABLE MEMORY
(1995-02-01)
LEE, CY
;
YANG, RY
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交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
The paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well known LZ77 algorithm, The architecture mainly consists of three units, namely, content addressable memory, match-logic unit, and output-stage unit, The content-address-memory unit generates a Set of hits signals which identify those positions whose symbols in a specified window are the same as the input symbol. These hits signals are then passed to the match-logic unit which determines both match length and location to form the kernel of compressed data, These two items are then passed to the output-stage unit for packetisation before being sent out. Simulation results show that, based on a 0.8 mu m CMOS process technology, a clock speed of up to 50 MHz can be achieved for a VLSI design containing a 2K buffer size. This implies that the developing data compressor chip can handle many real-life applications, such as in high-speed data storage and networking systems,
MICROCRYSTALLINE beta-SIC GROWTH ON SI BY ECR-CVD AT 500 degrees C
(1995)
CHENG, KL
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LIU, CC
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CHENG, HC
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LEE, CY
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YEW, TR
MINIMIZING THE MAKESPAN IN THE 3-MACHINE ASSEMBLY-TYPE FLOWSHOP SCHEDULING PROBLEM
(1993-05-01)
LEE, CY
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CHENG, TCE
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LIN, BMT
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資訊工程學系
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Department of Computer Science
This paper considers minimizing the makespan in the 3-machine assembly-type flowshop scheduling problem. After problem formulation, we present a proof to show that the general version of this problem is strongly NP-complete. We then discuss a few polynomially solvable cases of the problem and present the solution algorithms. Next, a branch and bound solution scheme is suggested. Finally, three heuristics to find approximate solutions to the general problem are proposed and their error bounds are analyzed.
MULTIPROCESSOR SCHEDULING WITH INTERPROCESSOR COMMUNICATION DELAYS
(1988-06-01)
LEE, CY
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HWANG, JJ
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CHOW, YC
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ANGER, FD
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管理科學系
SCHEDULING PRECEDENCE GRAPHS IN SYSTEMS WITH INTERPROCESSOR COMMUNICATION TIMES
(1989-04-01)
HWANG, JJ
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CHOW, YC
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ANGER, FD
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LEE, CY
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交大名義發表
SEMI-SYSTOLIC ARRAY BASED MOTION ESTIMATION PROCESSOR DESIGN
(1995)
LU, MC
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LEE, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
VLSI IMPLEMENTATION OF AN M-ARRAY IMAGE FILTER BASED ON SHIFT REGISTER ARRAY
(1993-11-01)
LEE, CY
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TSAI, JM
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HSU, SC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel VLSI solution for sorting input samples in the transform domain to achieve real-time performance for image/video applications. The sorting is based on a dedicated memory containing so-called bar-chart information. The required value, such as median, can be generated from MSB to LSB sequentially by successively evaluating each bit of the memory content. In the architecture design, the dedicated memory is realized by (1) level control unit and (2) shift register arrays. To speed up the formation of bar-charts, the level control unit provides parallel control signals to the shift register arrays. Moreover, such an architecture can easily be updated when running any order operations are concerned. Our current design can handle at most 25 input samples with word-length of 8 bits, and the resultant IC shows that a 25-MHz clock rate can be achieved and the chip area is 0.69 x 0.56 cm2.