Browsing by Author "LEI, TF"

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A DOUBLE METAL STRUCTURE PT/AL/N-INP DIODE
(1995-07-01)
HUANG, WC
;
LEI, TF
;
LEE, CL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A NOVEL PLANARIZATION OF TRENCH ISOLATION USING POLYSILICON REFILL AND ETCHBACK OF CHEMICAL-MECHANICAL POLISH
(1995-10-01)
CHENG, JY
;
LEI, TF
;
CHAO, TS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The planarization of trench isolation refilled by deposition oi polysilicon was investigated. Results show that the planarization by RIE etching has poor surface planarity. On the other hand, an excellent surface planarity can be achieved by the CMP process resulting from the high etching selectivity of polysilicon to nitride. This simple process provides a very promising candidate for trench isolation.
A NOVEL PLANARIZATION OF TRENCH ISOLATION USING POLYSILICON REFILL AND ETCHBACK OF CHEMICAL-MECHANICAL POLISH
(1995-10-01)
CHENG, JY
;
LEI, TF
;
CHAO, TS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The planarization of trench isolation refilled by deposition oi polysilicon was investigated. Results show that the planarization by RIE etching has poor surface planarity. On the other hand, an excellent surface planarity can be achieved by the CMP process resulting from the high etching selectivity of polysilicon to nitride. This simple process provides a very promising candidate for trench isolation.
A REAL-TIME C-V MEASUREMENT CIRCUIT FOR MOS CAPACITORS UNDER CURRENT STRESSING
(1991-08-01)
LEE, CL
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LEI, TF
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HO, JH
;
WANG, WT
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電子工程學系及電子研究所
A dynamic large signal C-V measurement circuit is presented to measure real time C-V characteristics of a MOS structure under current stressing conditions. The real time information on the generation and filling of traps and surface states can thus be obtained. With this circuit it has been shown that, for an Al-gate MOS structure, charges on traps and interface surface states recover immediately after the stressing is removed.
A SIMPLE METHOD FOR SINGLE-FREQUENCY OPERATION AND AMPLITUDE-STABILIZATION AND FREQUENCY-STABILIZATION OF AN INTERNAL-MIRROR HE-NE-LASER
(1985)
PAN, CL
;
KUO, CC
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HSIEH, TC
;
LEI, TF
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交大名義發表
A STUDY OF THE INTERFACIAL LAYER OF AL AND AL(1-PERCENT SI)-SI CONTACTS USING A ZERO-LAYER ELLIPSOMETRY MODEL
(1992-11-01)
CHAO, TS
;
LEE, CL
;
LEI, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, the interfacial layer of the Al-Si and Al(1% Si) Si contacting system annealed at different temperatures have been studied using ellipsometry incorporated with a zero-layer model. The results show that the thickness of the interfacial P+ layer between Al or Al(1% Si) and the Si-substrate increases with the annealing temperature and the thickness of the P+-layer of the Al(1% Si)-Si system is generally lower than that of the Al-Si system. Also, the fraction of Al in the interfacial layer decreases with the annealing temperature for the Al-Si system, but increases for the Al(1% Si)-Si system. The electrical measurements show that the interface of the Al(1% Si)-Si contact is more stable than that of the Al-Si contact.
A SWITCHING DEVICE OF A PN JUNCTION STRUCTURE WITH 2 LAYERS OF THIN OXIDE
(1989-06-01)
CHANG, DCY
;
LEE, CL
;
LEI, TF
;
交大名義發表
;
電控工程研究所
A VERTICAL KELVIN TEST STRUCTURE FOR MEASURING THE TRUE SPECIFIC CONTACT RESISTIVITY
(1986-04-01)
LEI, TF
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LEU, LY
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LEE, CL
;
交大名義發表
;
電控工程研究所
AN ANALYTICAL MODEL FOR THE ABOVE-THRESHOLD CHARACTERISTICS OF POLYSILICON THIN-FILM TRANSISTORS
(1995-07-01)
CHERN, HN
;
LEE, CL
;
LEI, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An analytical model for the above-threshold characteristics of long-channel, small-grain and thin channel polysilicon thin film transistors (TFT's) is presented. This model is constructed by considering the barrier potential and the carrier trapping effect at grain boundaries of the channel. A band tail state located at E(c) - 0.15 eV is taken into account to simulate the I-V characteristics. Based on the model, the theoretically simulated results show good agreement with the experimental data of the plasma-passivated and unpassivated TFT devices in a wide range of the gate, drain biases and the temperature. The correlation of the transconductance to the gate bias is also investigated, It is found that the decrease of grain-boundary barrier potential with the gate voltage enhances the transconductance, while this enhancement effect becomes insignificant and causes the decrease of the transconductance at the high gate bias.
AN MINPIM STRUCTURE MIXING DEVICE
(1989-04-01)
CHANG, DCY
;
LEE, CL
;
LEI, TF
;
交大名義發表
;
電控工程研究所
AN SCR WITH SIMPLE MIS STRUCTURE
(1990-12-01)
CHANG, DCY
;
LEE, CL
;
LEI, TF
;
電控工程研究所
;
Institute of Electrical and Control Engineering
A device to work as an SCR with a simple MIS p-n Structure is proposed and demonstrated. It employs two junction diodes, with a thin oxide layer grown prior to metallization. This device can act as a triac when a bi-directional ac voltage is applied, while acts as an SCR when a bias voltage is applied to the N-substrate.
ANOMALOUS DOPING BEHAVIOR OF IN-SITU BORON-DOPED POLYCRYSTALLINE SILICON DEPOSITED BY ULTRAHIGH-VACUUM CHEMICAL-VAPOR-DEPOSITION
(1993-09-13)
LIN, HC
;
LIN, HY
;
CHANG, CY
;
LEI, TF
;
WANG, PJ
The deposition of in situ heavily boron-doped polycrystalline silicon (poly-Si) films was studied using an ultrahigh vacuum/chemical vapor deposition system. Fully activated carrier concentrations up to 3X10(20) cm-3 were obtained for the as-deposited films grown at 550-degrees-C. For boron concentration beyond this level, the crystallinity of poly-Si films degraded with increasing boron concentration, which resulted in an anomalous rise in resistivity. This crystallinity degradation occurred at a higher rate for films grown on a SiO2 surface than those grown on an undoped poly-Si surface. It is attributed to the preferential adsorption of boron atoms on the SiO2 surface. Under a high B2H6 flux condition, a large amount of boron atoms would accumulate on the SiO2 Surface before the formation of Si nuclei, and thus disturbs the subsequent film deposition and grain growth processes.
CHARACTERISTICS OF BORON-DIFFUSION IN POLYSILICON SILICON SYSTEMS WITH A THIN SI-B LAYER AS DIFFUSION SOURCE
(1995-02-01)
CHEN, TP
;
LEI, TF
;
LIN, HC
;
CHANG, CY
;
電子工程學系及電子研究所
A new material, Si-B layer, as boron diffusion source for polysilicon/silicon systems, has been investigated. The Si-B layer was deposited on polysilicon in an ultrahigh vacuum chemical vapor deposition (UHV/CVD) system at 550 degrees C. The characteristics of boron diffusion in Si-B layer/polysilicon/silicon systems have been investigated by using secondary ion mass spectroscopy (SIMS) and cross-sectional transmission electron microscopy (XTEM). To remove the Si-B layer after the drive-in step, the Si-B layer was oxidized completely during thermal drive-in stage and removed with a diluted hydrofluoric acid. The effects of thermal oxidation of Si-B layer on boron diffusion profiles and polysilicon structures were analyzed. It was found that the boron profiles within the polysilicon are slightly dependent on the oxidation of Si-B layer. Moreover, the polysilicon grain size for Si-B layer source were enlarged, as compared with conventional BF2+-implanted polysilicon source. It is attributed to the effects of the gettering of oxygen impurity by the Si-B layer and secondary grain growth during Si-B layer oxidation. In addition, the boron diffusion profiles in the silicon substrate for Si-B layer source exhibited a more shallow junction depth and less sensitivity to the thermal budget, as compared with BF2+-implanted polysilicon source. This is considered to be the effect of the smaller surface concentration, C-s, in the silicon substrate for Si-B layer source.
CHARACTERISTICS OF POLYCRYSTALLINE FILMS GROWN BY ULTRAHIGH-VACUUM CHEMICAL-VAPOR-DEPOSITION SYSTEM
(1995-12-01)
LIN, HY
;
LEI, TF
;
LIN, HC
;
CHANG, CY
;
TWU, RC
In situ boron-doped polycrystalline Si1-xGex (poly-Si1-xGex) films deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) system were characterized. Optimum fitted values of grain boundary trap state densities, 4.0 x 10(12) cm(-2) and 4.9 x 10(12) cm(-2) were obtained for poly-Si and poly-Si0.79Ge0.21, respectively. The extracted average carrier concentration in the grain agrees with secondary ion mass spectroscopy (SIMS) analysis. In turn, we found that these films are suitable Hall elements to sense magnetic field. Experimental results show that the sensitivity decreased with the increasing input current, which can be well explained using the thermionic emission theory. Finally, we use these films to fabricate thin film transistors.
CHARACTERISTICS OF POLYSILICON CONTACTED SHALLOW JUNCTION DIODE FORMED WITH A STACKED-AMORPHOUS-SILICON FILM
(1993-10-01)
WU, SL
;
LEE, CL
;
LEI, TF
;
CHANG, HC
;
電子工程學系及電子研究所
A high-performance shallow junction diode formed with a stacked-amorphous-silicon (SAS) film is presented. Since the boundaries of stacked silicon layers and the poly/mono silicon interface act as a diffusion barrier for implanted dopants, the junction depth of SAS emitter contacted diode is about 500 angstrom shallower than that of the as-deposited polysilicon (ADP) emitter contacted diode. The fabricated SAS emitter contacted diodes exhibited a very low reverse leakage current (less-than-or-equal-to 1 nA/cm2 at -5 V) and a forward.ideality factor m almost-equal-to 1.001 over 7 decades on a log scale. The reverse I-V characteristics were found to be nearly independent of the reverse voltage from the room temperature to 200-degrees-C, and it was also found that the leakage current was due almost completely to the diffusion current. The plots of the diode leakage current versus the perimeter to area ratio showed that the periphery generation current only contributed a small portion to the total leakage. The processing temperature for the SAS emitter contacted p+-n diode can be as low as 600-degrees-C.
CHARACTERISTICS OF TOP-GATE THIN-FILM TRANSISTORS FABRICATED ON NITROGEN-IMPLANTED POLYSILICON FILMS
(1995-12-01)
YANG, CK
;
LEI, TF
;
LEE, CL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The electrical characteristics of top-gate thin-film transistors (TFT's) fabricated on the nitrogen-implanted polysilicon of the doses ranging from 2 x 10(12)-2 x 10(14) ions/cm(2) were investigated in this work, The experimental results showed that nitrogen implanted into polysilicon followed by an 850 degrees C 1 h annealing step had some passivation effect and this effect was much enhanced by a following H-2-plasma treatment. The threshold voltages, subthreshold swings, ON-OFF current ratios, and field effect mobilities of both n-channel and p-channel TFT's were all improved, Moreover, the hot-carrier reliability was also improved, A donor effect of the nitrogen in polysilicon was also found which affected the overall passivation effect on the p-channel TFT's.
CHARACTERIZATION OF SEMIINSULATING POLYCRYSTALLINE SILICON PREPARED BY LOW-PRESSURE CHEMICAL-VAPOR-DEPOSITION
(1993-09-01)
CHAO, TS
;
LEE, CL
;
LEI, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We employed the multiple angle incident ellipsometer to study the growth mechanism and optical properties of semi-insulating polycrystalline silicon (SIPOS) films deposited by the low-pressure chemical vapor deposition (LPCVD) technique. A significant difference of the imaginary part of the refractive index between film at the edge and those in the central region of the wafer was observed. Our analyses showed that it was consistent with the N2O depletion model. This N2O depletion phenomenon was confirmed by Auger analysis. Moreover, we found that spatial N2O depletion at the edge of the wafer was greatly influenced by the flow rate of SiH4 to N2O gases. Excessively high N2O flow rate suppressed the silicon microcrystal resulting in a thinner SIPOS film.
CHARACTERIZATION OF ULTRATHIN OXIDE PREPARED BY LOW-TEMPERATURE WAFER LOADING AND NITROGEN PREANNEALING BEFORE OXIDATION
(1992-08-15)
WU, SL
;
LEE, CL
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LEI, TF
;
LIANG, MS
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電子工程學系及電子研究所
In this study, we report a high-performance ultrathin oxide (almost-equal-to 80 angstrom) prepared by a low-temperature wafer loading and N2 preannealing before oxidation. This recipe can reduce native oxide thickness and thermal stress compared to the conventional oxidation recipe. The high-resolution transmission electron microscopy reveals that the SiO2/Si interface is atomically flat, and a thin crystalline-like oxide layer about 7 angstrom exists at the interface. Oxides prepared by the proposed recipe show a very high dielectric breakdown field (greater-than-or-equal-to 16 MV/cm) and a very low interface state density (N(it) almost-equal-to 3 X 10(9) eV-1 cm-2 at midgap). The effective barrier height at cathode derived from the slopes of log(J(g)/E2(ox)2 vs 1/E(ox) and t(bd) vs 1/E(ox) plots is about 3.9 eV, instead of 3.2 eV for the control sample. It also shows a better immunity to the charge trapping and interface state generation under high-field stressing, and superior time-dependent dielectric breakdown characteristics.
CORRELATION OF POLYSILICON THIN-FILM-TRANSISTOR CHARACTERISTICS TO DEFECT STATES VIA THERMAL ANNEALING
(1994-03-01)
CHERN, HN
;
LEE, CL
;
LEI, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Based on the response of electrical characteristics of hydrogenated polysilicon thin-film transistors (TFT's) to post-hydrogenation thermal annealing, the relationship of device parameters to deep states and tail states are distinguished. The deep states which affect the threshold voltage and subthreshold swing recover quickly, while the tail states which influence the leakage current and field effect mobility respond to the thermal annealing only after the annealing temperature exceeds 375 degrees C for 30 min.
CROSSOVER PHENOMENON IN OXIDATION RATES OF THE (110) AND (111) ORIENTATIONS OF SILICON IN N2O
(1995-03-01)
CHAO, TS
;
LEI, TF
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電控工程研究所
;
Institute of Electrical and Control Engineering
Growth mechanisms of three different orientations Si wafer oxidized in N2O have been investigated in this study. A thickness crossover phenomenon in oxidation rates was found for orientations (110) and (111) at a critical oxide thickness 150 Angstrom. From our results, this phenomenon is closely related with the initial native oxide before oxidation.