Browsing by Author "LIN, CZ"

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A DATA DRIVEN HYBRID COMPUTER ARCHITECTURE
(1992-09-01)
TSENG, CC
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LIN, CZ
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HWANG, JK
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LIN, KT
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資訊工程學系
The combination of dataflow and von Neumann execution models is a recent trend in designing high speed computers. In this paper, a data-driven hybrid computer architecture is presented. Dynamic data-driven execution principle, instead of program counter, is used to control the execution of instructions in a von Neumann style pipelined architecture. Unlike normal dynamic dataflow architecture, data are explicitly stored in memory and their memory locations are used as tags. Matching operation is accomplished by a simple comparison of two counters and no special matching unit is required. With an ideal memory system, no bubble may occur in the pipe if sufficient parallelism exists in the program. Furthermore, multiple memory modules and short-circuit scheme are used to fulfill simultaneous memory requests. An extensive simulator has been designed to evaluate the proposed architecture. The experimental results show that the proposed architecture is promising.
ANALYZING CACHE PERFORMANCE ON MULTI-STREAM EXECUTION PROCESSOR
(1993)
LIN, CZ
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TSENG, CC
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CHUNG, CP
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資訊工程學系
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Department of Computer Science
DESIGN OF AN EFFICIENT DATA-DRIVEN PIPELINED COMPUTER ARCHITECTURE
(1995-07-01)
LIN, CZ
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TSENG, CC
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CHI, KH
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交大名義發表
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資訊工程學系
The combination of dataflow and von Neumann execution models is a recent trend in the design of high performance computers. In this paper, a data-driven hybrid computer architecture is presented. Instead of a program counter, the principle of dynamic data-driven execution is used to control the execution of instructions in a von Neumann-style pipeline architecture. One of the operands of each dyadic instruction is explictly stored in memory, and the memory locations of the stored operands are used as tags. Matching is accomplished by simply checking a present flag and no special matching unit is required. No bubbles will occur in the pipe if sufficient parallelism exists in the program. Experimental results show that the proposed architecture outperforms two previously proposed architectures.