Browsing by Author "Lai, Tai-Xiang"

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Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in a 0.25-mu m salicided CMOS process
(2006)
Ker, Ming-Dou
;
Lai, Tai-Xiang
;
電機學院
;
College of Electrical and Computer Engineering
In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of Cable Discharge Event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been experimentally investigated in detail. All CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.25-mu m salicided CMOS process to find optimum layout rules for CDE protection. From the measured results, the CDE robustness of CMOS devices is much worse than their HBM ESD robustness.
Method to evaluate Cable Discharge Event (CDE) reliability of integrated circuits in CMOS technology
(2006)
Lai, Tai-Xiang
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface in field applications. The transmission line pulsing (TLP) system has been the most popular method to observe electric characteristics of the device under human-body-model (HBM) electrostatic discharge (ESD) stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate CDE reliability of the Ethernet integrated circuits, and the results are compared with the conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-mu m CMOS technology is worse than its HBMESD robustness.
Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event
(2005)
Lai, Tai-Xiang
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Cable Discharge Event (CDE) has been the main cause which damages the Ethernet interface. The transmission line pulsing (TLP) system has been the most important method to observe electric characteristics of the device under human-body-model (HBM) ESD stress. In this work, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of CDE on the Ethernet integrated circuits, and the results are compared with conventional 100-ns TLP system. The experimental results have shown that the CDE robustness of NMOS device in a 0.25-mu m CMOS technology is much worse than its HBM electrostatic discharge robustness.
The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process
(2007)
Chang, Wei-Jen
;
Ker, Ming-Dou
;
Lai, Tai-Xiang
;
Tang, Tien-Hao
;
Su, Kuan-Cheng
The ESD robustness on different device structures and layout parameters of high-voltage (HV) NMOS has been investigated in 40-V CMOS process with silicon verification. It was demonstrated, that a specific structure of HV n-type silicon controlled rectifier (HVNSCR) embedded into HV NMOS without N-drift implant in the drain region has the best ESD robustness. Moreover, due to the different current distributions in HV NMOS and HVNSCR, the trends of the TLP-measured It2 under different spacings from the drain diffusion to polygate are different.