Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in a 0.25-mu m salicided CMOS process

Abstract

In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of Cable Discharge Event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been experimentally investigated in detail. All CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.25-mu m salicided CMOS process to find optimum layout rules for CDE protection. From the measured results, the CDE robustness of CMOS devices is much worse than their HBM ESD robustness.