Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in a 0.25-mu m salicided CMOS process

dc.citation.epage	634	en_US
dc.citation.spage	633	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Lai, Tai-Xiang	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.date.accessioned	2014-12-08T15:25:06Z
dc.date.available	2014-12-08T15:25:06Z
dc.date.issued	2006	en_US
dc.description.abstract	In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of Cable Discharge Event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been experimentally investigated in detail. All CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.25-mu m salicided CMOS process to find optimum layout rules for CDE protection. From the measured results, the CDE robustness of CMOS devices is much worse than their HBM ESD robustness.	en_US
dc.identifier.isbn	0-7803-9498-4	en_US
dc.identifier.journal	2006 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 44TH ANNUAL	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/17478
dc.identifier.wosnumber	WOS:000240855800113
dc.language.iso	en_US	en_US
dc.title	Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in a 0.25-mu m salicided CMOS process	en_US
dc.type	Proceedings Paper	en_US

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