Browsing by Author "Lee, CL"

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A behavior-level fault model for the closed-loop operational amplifier
(2000-09-01)
Chang, YJ
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Lee, CL
;
Chen, JE
;
Su, CC
;
電子工程學系及電子研究所
In this paper, a simple behavior-level fault model, which is able to represent the faulty behavior of the closed-loop operational amplifier (OP), is presented. The fault model, derived from the macro equivalent circuit of the OP but verified with transistor level simulation, consists of the offset fault and the limited-current fault. It can represent the faulty behavior of the dosed loop OP of all the transistor parametric (soft) faults and many of the catastrophic (hard) faults. Due to its simplicity, the proposed fault model (1) significantly reduces the complexity of fault simulation, and (2) makes closed-form analysis of the faulty behavior of the closed loop OP feasible when the closed loop OP is used as a basic building block of a complicated circuit. Although derived for DC, it can also be applied to AC fault analysis.
A cocktail approach on random access scan toward low power and high efficiency test
(2005)
Lin, SP
;
Lee, CL
;
Chen, JE
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Scan design, providing a good test solution to sequential circuits, suffers large data volume, long test time and high test power problem. Recently, the Random Access Scan (RAS) scheme offers a solution to alleviate the above problems [6]. In this paper, based on RAS, a cocktail scan scheme is proposed and demonstrated to improve the test efficiency significantly. The scheme adopts a two-phase approach, firstly by using a cycle random scan test with a few random seed patterns to test the DUT and secondly, by using the RAS mechanism to test the circuit. Due to employment of a revised process and several strategies, namely, Test Response Abundant, Constrained Static Compaction, and Bit Propagation Before Test Vector Dropping, it is very effective in reducing bit flipping and test data volume, consequently, the test application time and power. Experimental results show that the scheme can achieve 86% reduction in test data volume and 10 times of speedup in test application time.
A compiled-code parallel pattern logic simulator with inertial delay model
(1999-11-01)
Huang, KC
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Lee, CL
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Chen, JE
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a parallel pattern compiled code logic simulator which can handle the transport delay as well as the inertial delay of the logic gate. It uses Potential-Change Frame, incorporating inertial functions, to execute event-canceling operation of gates, thus eliminating the conventional time wheel mechanism. As a result, it can adopt the parallel pattern strategy to increase the simulation speed. Furthermore, it is a compiled code simulator, which further improves its performance. Experimental results show that it significantly surpasses the conventional time wheel event-driven simulator in terms of simulation speed. In addition, it is also found that a significant percentage (27%) of hazards can be eliminated when the effect of the inertial delay is considered in the simulation.
A fast and sensitive built-in current sensor for IDDQ testing
(1996)
Lu, CW
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Lee, CL
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Chen, JE
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high speed circuit scheme for driving field emission array
(1996)
Lu, CW
;
Lee, CL
;
Huang, JM
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交大名義發表
;
電子工程學系及電子研究所
The field emission array (FEA), when used as a display device, requires a scanning driving circuit. Due to the large FEA capacitance (typically 5 pF for one pixel), the driving circuit is usually slow. In this work, a new driving circuit, which employs the voltage controlled current source (VCCS), overcomes the above-mentioned problem, thus can reach a high driving speed. In addition, the circuit has the advantages of a uniform current driving, the gray level control and the low power consumption.
A low-power high-speed class-AB buffer amplifter for flat-panel-display application
(2002-04-01)
Lu, CW
;
Lee, CL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A low-power, high-speed, but with a large input dynamic range and output swing class-AB output buffer circuit, which is suitable for the flat-panel display application, is proposed. The circuit employs an elegant comparator to sense the transients of the input to turn on charging/discharging transistors, thus draws little current during static, but has an improved driving capability during transients. It is demonstrated in a 0.6 mum CMOS technology.
A methodology for fault model development for hierarchical linear systems
(2000)
Huang, YC
;
Lee, CL
;
Lin, JW
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Chen, JE
;
Su, CC
In this paper, a methodology to develop fault models for hierarchical linear systems which are composed of operational amplifiers(OP) is demonstrated and presented. The methodology, at first, presents a transfer function model for the open-loop OP based on analysis of element faults at the transistor level. Then it derives a transfer function model for the closed loop OP based on the derived open-loop OP level model, again a higher level fault model for a module which is composed of closed loop OPs. The models can handle ac faults. The benchmark state-variable filter is used as an example to demonstrate for this methodology. an application of the derived models to Monte-Carlo simulation to save computation time is also demonstrated.
A multiple-sequence generator based on inverted nonlinear autonomous machines
(1996-09-01)
Lee, CL
;
Sheu, ML
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new multiple-sequence generator scheme to generate a set of deterministic ordered sequence of patterns followed by random patterns is presented in this paper. This scheme is based on an inverted nonlinear autonomous machine which utilizes a two-dimension-like LFSR with nonlinear inverters. A systematic procedure is also presented to obtain the autonomous machine which is more regular in the structure and utilizes less hardware. The generated deterministic sequence of patterns, which may have ordered and repeated patterns, and the random patterns are applicable to sequential circuit testing.
A multiple-sequence generator based on inverted nonlinear autonomous machines
(1996-09-01)
Lee, CL
;
Sheu, ML
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new multiple-sequence generator scheme to generate a set of deterministic ordered sequence of patterns followed by random patterns is presented in this paper. This scheme is based on an inverted nonlinear autonomous machine which utilizes a two-dimension-like LFSR with nonlinear inverters. A systematic procedure is also presented to obtain the autonomous machine which is more regular in the structure and utilizes less hardware. The generated deterministic sequence of patterns, which may have ordered and repeated patterns, and the random patterns are applicable to sequential circuit testing.
A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC
(2004)
Chen, GX
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Lee, CL
;
Chen, JE
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a new BIST scheme for the Digital-to-Analog Converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. A 8-bit DAC BIST circuit is designed for demonstration.
A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI
(1998)
Lu, CW
;
Lee, CL
;
Chen, JE
;
Su, CC
;
電子工程學系及電子研究所
In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.
A new path delay test scheme based on path delay inertia
(2004)
Chen, CL
;
Lee, CL
;
Wu, MS
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes a new path delay test scheme based on path delay inertia. The scheme only applies pulses of specified widths, which are proportional to path delays, to paths-under-test. It is simple, eliminating the conventional two-pattern test for delay faults. Issues, such as sensitivity of applied pulse widths w.r.t. path delay, related with the scheme were studied and an experimental chip was implemented to demonstrate the scheme.
A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset
(1996-05-01)
Lai, CS
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Lee, CL
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Lei, TF
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Chern, HN
;
電子工程學系及電子研究所
A novel device structure for the vertical bottom polysilicon gate thin film transistor (TFT) with a self-align offset drain is proposed and demonstrated, The new VTFT allows a deep-submicron channel length, which is determined by the thickness of the active polysilicon film, not by the lithographic system resolution, The self-alignment offset drain reduces the leakage current, as a result, it exhibits good device performance.
A physical model for the hysteresis phenomenon of the ultrathin ZrO2 film
(2002-10-01)
Wang, JC
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Chiao, SH
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Lee, CL
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Lei, TF
;
Lin, YM
This work studies and presents an inner-interface trapping physical model for the ultra-thin (effective oxide thickness=15 Angstrom) zirconium oxide (ZrO2) film to explain its hysteresis phenomenon. The shift of the capacitance-voltage characteristics swept from accumulation to inversion and then swept back with light illumination is about 110 mV, which is larger than the shift without light illumination (similar to45 mV). The mobile ion effect is obviated using bias-temperature stress measurement. The proposed model successfully explains not only the phenomenon but also the thickness effect for the capacitance-voltage characteristics and the different turn-around voltages of the current density-voltage characteristics of the zirconium dielectrics. (C) 2002 American Institute of Physics.
A physical simulation model for field emission triode
(1998-10-01)
Lu, CW
;
Lee, CL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A simple but accurate physical model, which can be incorporated into circuit simulation programs such as SPICE for the field emission triode (FET), is developed. The model is based on the Fowler-Nordheim (F-N) current density-electric field (J-E) relationship. An electric field form is adopted to calculate the current density distribution along the surface of the sphere-shape tip. The cathode current is obtained by integration of the current density over the emission surface. The gate current is derived by the same integration, but over part of the emission area. A procedure to extract the values for the parameters of the model is also given. The model and the procedure has been applied to experimental devices to demonstrate its accuracy.
A physical simulation model for field emission triode
(1998-10-01)
Lu, CW
;
Lee, CL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A simple but accurate physical model, which can be incorporated into circuit simulation programs such as SPICE for the field emission triode (FET), is developed. The model is based on the Fowler-Nordheim (F-N) current density-electric field (J-E) relationship. An electric field form is adopted to calculate the current density distribution along the surface of the sphere-shape tip. The cathode current is obtained by integration of the current density over the emission surface. The gate current is derived by the same integration, but over part of the emission area. A procedure to extract the values for the parameters of the model is also given. The model and the procedure has been applied to experimental devices to demonstrate its accuracy.
A scalable architecture for differentiated services
(2002)
Lee, CL
;
Chen, JR
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Chen, YC
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交大名義發表
;
National Chiao Tung University
Differentiated services (DiffServ) model is a potential solution for providing quality of services (QoS) on the Internet. In this paper, we propose a scalable architecture that fulfills the design philosophy of the DiffServ model. Different from other existing architectures, our proposed architecture puts complexity on edge routers so that core routers do not need to support any specific function for service differentiation. Further, the proposed architecture only needs few additional functions in edge routers. Thus its deployment is simpler than most existing architectures. We also address how to achieve weighted proportional fairness solely by edge routers.
A scan matrix design for low power scan-based test
(2005)
Lin, SP
;
Lee, CL
;
Chen, JE
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
For the scan design, the circuit under test (CUT) in the test mode usually has larger switching activity than in the function mode, causing excessive power dissipation. In this paper, we propose a new Scan Matrix (SM) architecture for the scan-based design to achieve low power testing. The scan flip-flops are connected in a matrix style for test and its addressing is controlled by two ring generators during pattern scanning in. Unlike the traditional scan, for which scan-in data need to pass through a long path and many scan flip-flops switch simultaneously, the proposed approach dynamically forms a low-power scan path to reduce test energy and peak power during shift significantly. The architecture is scalable for large designs and has minimal circuit performance penalty. Experimental results show that, for some larger designs, nearly 99% power savings have been achieved.
A simplified approach based on source control for ATM ABR service
(2001-08-15)
Lee, CL
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Chen, YC
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Chen, JR
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資訊工程學系
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Department of Computer Science
The available bit rate (ABR) service is designed to provide efficient support of data traffic in ATM networks. A variety of rate-based flow control approaches have been proposed to support ABR service. Most of these approaches improve both the fairness among active connections and the link utilization by putting more and more complexity into a switch. In this article, we propose a flow control approach in which part of rate-calculation work is moved from switches to end-systems. As a result, the proposed approach reduces the rate-calculation effort in the switch. This may reduce the switch complexity and thus the implementation cost. Furthermore, it mitigates the difficulty for setting the measurement interval in switches. as well as features lower and more stable queue occupancy in the network. Simulation results are presented to demonstrate that the proposed approach achieves better performance than ERICA +, a well-known switch algorithm. (C) 2001 Elsevier Science B.V. All rights reserved.
A SPICE simulation model for field emission triode
(1996)
Lu, CW
;
Lee, CL
;
Huang, JM
;
交大名義發表
;
電子工程學系及電子研究所
In this work, a simple but accurate circuit model, which can be incorporated into circuit simulation programs such as SPICE, for field emission triode (FET) is developed. The model is based on the Fowler-Nordheim (F-N) J-E relationship but takes into account the charge distribution on the surface of the tip of the device. A procedure is also developed to extract the parameters of the model.