A new path delay test scheme based on path delay inertia

Abstract

This paper proposes a new path delay test scheme based on path delay inertia. The scheme only applies pulses of specified widths, which are proportional to path delays, to paths-under-test. It is simple, eliminating the conventional two-pattern test for delay faults. Issues, such as sensitivity of applied pulse widths w.r.t. path delay, related with the scheme were studied and an experimental chip was implemented to demonstrate the scheme.