A new path delay test scheme based on path delay inertia

dc.citation.epage	144	en_US
dc.citation.spage	140	en_US
dc.contributor.author	Chen, CL	en_US
dc.contributor.author	Lee, CL	en_US
dc.contributor.author	Wu, MS	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:25:45Z
dc.date.available	2014-12-08T15:25:45Z
dc.date.issued	2004	en_US
dc.description.abstract	This paper proposes a new path delay test scheme based on path delay inertia. The scheme only applies pulses of specified widths, which are proportional to path delays, to paths-under-test. It is simple, eliminating the conventional two-pattern test for delay faults. Issues, such as sensitivity of applied pulse widths w.r.t. path delay, related with the scheme were studied and an experimental chip was implemented to demonstrate the scheme.	en_US
dc.identifier.isbn	0-7695-2235-1	en_US
dc.identifier.issn	1081-7735	en_US
dc.identifier.journal	13TH ASIAN TEST SYMPOSIUM, PROCEEDINGS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/18183
dc.identifier.wosnumber	WOS:000225878400023
dc.language.iso	en_US	en_US
dc.title	A new path delay test scheme based on path delay inertia	en_US
dc.type	Proceedings Paper	en_US

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