Browsing by Author "Lee, CY"

Now showing 1 - 20 of 123

A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm
(2000)
Chang, HC
;
Cheng, CY
;
Tsai, SH
;
Lee, CY
;
電子工程學系及電子研究所
A (204, 188) Reed-Solomon decoder for DVB application is presented. The RS decoder features an area-efficient Key Equation Solver using a novel decomposed Euclidean algorithm. We implement the RS decoder using 0.35 mum CMOS 1P4M standard cells, where the total gate count is about 16K similar to 17K. Test results show that the RS decoder chip can run up to 87MHz.
A 1.5-V, 2.4GHz CMOS low-noise amplifier
(2000)
Yang, JN
;
Lee, CY
;
Hsu, TY
;
Hsu, TR
;
Wang, CC
A 2.4GHz low noise amplifier has been designed in a standard CMOS 0-35 um process. The transistor model is Bsim3 for 0.35um process. The amplifier provides a forward gain of 33dB with a noise figure only 0.92dB while drawing 17mw from a 1.5 V supply. Design simulation results are presented In this paper.
A 1.75GHz inductor-less CMOS low noise amplifier with high-Q active inductor load
(2001)
Yang, JN
;
Cheng, YC
;
Hsu, TY
;
Hsu, TR
;
Lee, CY
A 1.75GHz CMOS inductor-less low noise amplifier with high-Q active inductor load using 0.35um. standard CMOS digital process is presented. In this low noise amplifier, the compact tunable high-Q active inductor load is connected to the common-gate configuration to improve the performance of the high power gain, low power consumption and simple matching characteristics. Not using any passive components is to reduce the area of chip and the complexity. HSPICE simulation has been performed to verify the performance of the designed low noise amplifier. It has been shown that the amplifier has a power gain of 24dB(S21), S11 of -31dB, S12 of -38.5dB and S22 of -21.4dB under 3.3V power supply with 9.3mW power consumption around at 1.75GHz center frequency. The experimental chip fabricated occupies 0.057x0.056 mm(2) chip area.
A 3.33Gb/s (1200,720) low-density parity check code decoder
(2005)
Lin, CC
;
Lin, KL
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm(2) 0.18 mu m silicon area. The other 0.13 mu m chip with the 10.24mm(2) core can further reach a 5.92Gb/s data rate under 1.02V supply.
A 528MS/s frequency synchronizer for OFDM-based UWB system
(2005)
Chen, LH
;
Chang, WC
;
Liu, HY
;
Lee, CY
;
電子工程學系及電子研究所
A novel frequency synchronizer is proposed for 528MHz OFDM-based UWB system. It can reduce 75% memory and 59% power consumption through a low-power scheme based on data. partition. Measured result shows the proposed design can achieve 528MSamples/s throughput in 0.18 mu m CMOS process.
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications
(2006-06-01)
Chen, PL
;
Chung, CC
;
Yang, JN
;
Lee, CY
;
電子工程學系及電子研究所
This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-mu m CMOS process with core area of 0.16 mm(2). Power consumption is 15 mW.@ 378 MHz with 1.8-V supply voltage.
A COMM baseband processor with robust synchronization for high-speed WLAN applications
(2004)
Liu, HY
;
Yu, YH
;
Lin, CC
;
Chung, CC
;
Hsu, TY
in this paper, a high-performance and low-cost COFDM baseband processor is presented. With algorithm exploration in channel estimation and phase error tracking, synchronization becomes more robust to enhance system performance. And better design SNR (1.35similar to7.16 dB) can be achieved compared to current solutions. Moreover through architectural exploration, the proposed baseband processor designed in 0.18 um CMOS process contains only 370 K logic gates and 3.3 K byte memory. Measurement results show that better hardware efficiency and performance enhancement is achieved for high-speed WLAN applications.
A compact software-controlled clock multiplier for SoC application
(2002)
Chen, PL
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A compact software-controlled clock multiplier for SoC application is presented in this paper. The control mechanism of clock multiplier includes frequency acquisition, phase acquisition and phase/frequency maintenance modes; these operations sequence are programmable. Our proposed clock multiplier is integrated with an 8-bit microcontroller in order to verify the proposed software-controlled mechanism. The control mechanism is sharing with the computing power of microcontroller. A proto-type chip has been implemented with 0.35 um 1P4M CMOS process that can operate from 25MHz to 80MHz. The multiplication factor can range from 2 to 128 and software instructions are less than 90 instructions. Thus it not only reduces the cost and design complexity of clock multiplier, but also offers particular advantages, especially when computing power is already available.
A constant power consumption CMOS LC oscillator using improved high-Q active inductor with wide rining-range
(2004)
Wu, MJ
;
Yang, JN
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An improved CMOS high-Q active inductor and a constant power consumption oscillator with wide tuning-range are presented. The inductor using one feedback resistor results in a gain to improve the Q-value of the inductor and tune the inductance (L). Based on this inductor, a negative resistance LC-tuned oscillator with constant power consumption and wide tuning-range has been designed. The simulation results show that the improved active inductor can achieve the maximum Q-value of 3500. The power consumption of a constant value around 10mW exists in the oscillator. This oscillator also depicts a reasonable phase noise performance of -91dBc/Hz at 600 kHz from 0.8GHz to 3GHz range. Furthermore, the deviation of the phase noise is as small as 6dBc/Hz during this tuning-range.
A cost-effective VLSI architecture for high-throughput sequential decoder
(1996)
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A design of CMOS broadband amplifier with high-Q active inductor
(2003)
Yang, JN
;
Cheng, YC
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A CMOS broadband amplifier with high-Q active inductor using 0.25um CMOS process is presented In this broadband amplifier, the compact high-Q active inductor is connected to the common-gate configuration to improve the performance of the high power gain, wide bandwidth, low power consumption and simple matching characteristics. Not using any passive inductor components is to be reduced the area of chip and the complexity. Advance Design System (ADS) simulator has been performed to verify the performance of the designed broadband amplifier It has been shown that the amplifier has a 20dB(S21) power gain in -3dB bandwidth, S11 of -17dB, S22 of -21 dB and noise figure (NF) of 8dB, under 2.5 V power supply with 18mW power consumption.*
A dual mode channel decoder for 3GPP2 mobile wireless communications
(2004)
Lin, CC
;
Shih, YH
;
Chang, HC
;
Lee, CY
;
電子工程學系及電子研究所
This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52Mb/s and 5.26Mb/s data rates respectively The memory access is reduced by the input caching scheme. And the system complexion is lowered by the efficient interleaver design. This chip is fabricated in a 0.18mum six-metal standard CMOS process, and the measured power dissipation is 83mW while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block.
A dynamic scaling FFT processor for DVB-T applications
(2004-11-01)
Lin, YW
;
Liu, HY
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer 1 are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-mum single-poly six-metal CMOS process with core area of 4.84 mm(2). Power dissipation is about 25.2 mW at 20 MHz.
A fast audio bit allocation technique based on a linear R-D model
(2002-08-01)
Lee, CY
;
Fang, YC
;
Chuang, HC
;
Wang, CN
;
Chiang, T
The MPEG-1 Layer III audio coding is most widespread digital audio format on the Internet. Its encoder is more complicated than the other layers., in the MPEG-I audio specification, where the bit allocation constitutes significant part of the total computational load. This paper describes a fast bit allocation technique using a novel linear model to compute the bitrate and the global gain of the inner loop (rate control loop) for the classic MP3 bit allocation problem. Estimated quantization noise is approximated with a binomial expansion for the adjustment of the scalefactors. This procedure reduces the outer loop iterations (distortion control loop) to one loop. Our bit allocation technique is about five times faster compared to the well-known LAME MP3 encoder. Based on the objective quality measure, total number of distorted bands, and average total noise-to-masking ratio (NMR), our experimental results show that there is significant improvement in speedup of the encoding process without noticeable audio quality degradation.
A fast audio bit allocation technique based on a linear R-D model
(2002-01-01)
Lee, CY
;
Fang, YC
;
Chuang, HC
;
Wang, CN
;
Chiang, TH
This paper describes a fast bit allocation technique using a novel linear model for the bitrate and the global gain of the inner loop in the classic MP3 bit allocation. The outer loop is approximated with a binomial expansion. Our technique is five times faster compared to the LAME MP3 encoder.
A generalized prediction method for modified memory-based high throughput VLC decoder design
(1999-06-01)
Lee, YS
;
Shieh, BJ
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Variable-length code (VLC) is the most popular data-compression technique which has been used in many data-compression standards, such as JPEG, MPEG-2, and H.263, In this paper, we present a new memory-based tree-search algorithm and very large scale integration architecture for VLC decoders which can achieve very high decoding throughput performance. Different coding tables can be implemented by simply changing the contents of the memory without changing the system hardware, The coding table is mapped onto a memory whose space requirement has been minimized by using a new tree data structure and efficient memory-mapping strategy. In addition, we break the recursive dependency of iterative searching operations by predicting method. The proposed algorithm and architecture can predict the searching node and perform parallel operations. As a result, the decoding throughput rate can be enhanced to about three to eight times more than previously announced architecture. The proposed architecture mainly consists of memory modules and simple arithmetic unit. Based on 0.6-mu m single poly triple metal CMOS technology and MPEG-2 VLC table-15, the decoder system achieves average decoding throughput rate of 720 Mbits/s at 3 V and a 100-MHz clock rate.
A high throughput context-based adaptive arithmetic codec for JPEG2000
(2002)
Ong, KK
;
Chang, WH
;
Tseng, YC
;
Lee, YS
;
Lee, CY
In JPEG2000 image compression standard, context-based arithmetic coding is adopted for improving compression rate. Efficient and high throughput codec: design is strongly required for handling high-resolution images. We propose an efficient architecture for context-based adaptive arithmetic coding, which can achieve high throughput performance. Based on parallel leading zeros detection and bit-stuffing handling, symbol can be encoded and decoded within one cycle. Therefore, throughput rate can be increased as high as codec operating frequency. The modified encoding and decoding flows are compatible with JPEG2000 standard. For 0.35u 1P4M CMOS technology, encoding and decoding rate can run up to 200Msymbol/sec and 175Msymbol/sec respectively. They are only cost 6.8K and 9.8K gate count. These high throughput performances can meet high-resolution real time application requirement.
A high throughput low cost context-based adaptive arithmetic codec for multiple standards
(2002)
Ong, KK
;
Chang, WH
;
Tseng, YC
;
Lee, YS
;
Lee, CY
For next generation image compression standard, context-based arithmetic coding is adopted for improving compression rate. Efficient and high throughput codec design is strongly required for handling high-resolution images. We propose an efficient codec architecture for context-based adaptive arithmetic coding, which exhibits low cost, low latency, and high throughput rate. In addition, it can be programmed for supporting multiple standards such as JPEG, JPEG2000, JBIG, and JBIG2 standards. It is exploiting three-pipeline stages architecture. Based on parallel leading zeros detection and bit-stuffing handling, symbol can be encoded and decoded within one cycle. Therefore, throughput rate can be increased as high as codec operating clock rate. For 0.35u 1P4M CMOS technology, both encoding and decoding rate can run up to 185Msymbol/sec. The AC codec only costs 12K gate count and 860um x 860um layout area. These performances can meet high-resolution real time application requirement.
A high throughput variable length decoder with modified memory based architecture
(1998)
Shieh, BJ
;
Lee, YS
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Variable-Length Code (VLC) is the most popular data compression technique. Therefore, a high throughput Variable-Length Decoder (VLD) is required in many applications. In this paper, we propose 2 simple modified methods which can increase throughput of memory-based two-bit structure Variable-Length Decoder system [1]*. The additional hardware of modified architecture is some control unit and a little memory space. The overall system still consists of control unit, arithmetic unit and memory. Simulation results show that the decompression rate based on 0.6um CMOS process and MPEG2 coding table-15 can achieve 720M bits/s with 100MHz clock rate.
A high-throughput memory-based VLC decoder with codeword boundary prediction
(2000-12-01)
Shieh, BJ
;
Lee, YS
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we present a high-throughput memory-based VLC decoder with codeword boundary prediction, The required information for prediction is added to the proposed branch models, Based on an efficient scheme, these branch models and the Huffman free structure are mapped onto memory modules, Taking the prediction information, the decompression scheme can determine the codeword length before the decoding procedure is completed. Therefore, a parallel-processor architecture can be applied to the VLC decoder to enhance the system performance. With a clock rate of 100 MHz, a dual-processor decoding process can achieve decompression rate up to 72.5 Msymbols/s on the average. Consequently, the proposed VLC decompression scheme meets the requirements of current and advanced multimedia applications.