Browsing by Author "Lee, Chia-Hsin"

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A New Methodology for Noise Sensor Placement Based on Association Rule Mining
(2016-01-01)
Hung, Yu-Hsiang
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Fang, Sheng-Hsin
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Chen, Hung-Ming
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Chen, Shen-Min
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Lin, Chang-Tzu
Due to near-threshold computing nowadays, voltage emergency is threatening our design margins very seriously. Noise sensors are inserted in order to prevent various integrity issues from happening during runtime. In this work, we use a new technique based on association rule mining to plan and place noise sensors. This new methodology can consider the miss rate (the probability of any node occurring voltage emergency without any detection by placed sensors) and simultaneously minimize the number of sensors utilized. The results show that our approach is very effective in converging the miss rate to zero by the least number of sensors. Compared with the state-of-the-art, we can reduce the number of sensors by half in benchmarks while the miss rate is comparable or even smaller than the prior work.
A Telescoping Synthesis of Chimeric Polyheterocycles through a Piperidine-Mediated Multicomponent Reaction
(2013-04-01)
Lee, Chia-Hsin
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Hsu, Wei-Shun
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Chen, Chih-Hau
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Sun, Chung-Ming
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應用化學系
A new piperidine-catalyzed Groebke-Bienayme-Blackburn (GBB) multicomponent reaction of 2-aminobenzimidazoles, methyl 2-formylbenzoate, and isocyanides has been explored. A facile and straightforward postmodification leads to isoquinolinone-embedded imidazo[1,2-a]benzimidazoles. Insight into a plausible mechanism is discussed and supported by X-ray crystal structure analysis.
An RDL-First Fan-Out Panel-Level Package for Heterogeneous Integration Applications
(2019-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Wang, Chun-Min
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Lee, Chia-Hsin
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Huang, Shin-Yi
Technologies of Fan-outpanel-level packaging (FOPLP) are studies in this paper. First, the warpage control of a molded panel is a crucial problem for FOWLP technology development. In this paper, finite element analysis (FEA) is applied to study the influence of back end of the line (BEOL) process-induced warpage, as well as characterization for simulation, and investigation of each single process. In our process, a liquid release material is coated onto a 370 mm x 470 mm glass carrier. After baking, three layers of redistribution layer (RDL), passivation, and Cu leads are fabricated on the panel with coating, exposing, developing, lithography, and electroplating processes. Silicon test chips with a size of 16 mm x 10 mm and micro solder bumps with a pitch of 90 mu m are thinned down to 150 mu m. Test chips are then flip-chip bonded onto glass carrier with pre-bond and reflow proces. After panel molding, a laser debonding method, another key technology advancement, is utilized for panel debond. Debond performance, which is directly related to laser parameter and panel-level package (PLP) structure, is critical. After debonding, the molded panel is cleaned, followed by dicing and OSP coating processes, and then the electrical performance of the interconnection is evaluated. Reliability tests at the component level, such as pre-condition, thermal cycling test (TCT), and unbiased HAST (uHAST), are performed. The demonstration of RDL-first PLP technology without interposers proves its great potential in heterogeneous integration applications.
An RDL-First Fan-out Wafer-level Package for Heterogeneous Integration Applications
(2018-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Shen, Wen-Wei
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Huang, Shin-Yi
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Kuo, Tzu-Ying
Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.
Effective Power Network Prototyping via Statistical-Based Clustering and Sequential Linear Programming
(2013-01-01)
Liu, Sean Shih-Ying
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Lee, Chieh-Jui
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Huang, Chuan-Chia
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Chen, Hung-Ming
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Lin, Chang-Tzu
In this paper, we propose a framework that automatically generates a power network based on given placed design and verifies the power network by the commercial tool without IR and Electro-Migration (EM) violations. Our framework integrates synthesis, optimization and analysis of power network. A deterministic method is proposed to decide number and location of power stripes based on clustering analysis. After an initial power network is synthesized, we propose a sensitivity matrix G(s) which is the correlation between updates in stripe resistance and nodal voltage. An optimization scheme based on Sequential Linear Programming (SLP) is applied to iteratively adjust power network to satisfy a given IR drop constraint. The proposed framework constantly updates voltage distribution in response to incremental change in power network. To accurately capture voltage distribution on a given chip, our power network models every existing power stripes and via resistances on each layer. Experimental result demonstrates that our power network analysis can accurately capture voltage distribution on a given chip and effectively minimize power network area. The proposed methodology is experimented on two real designs in TSMC 90nm and UMC 90nm technology respectively and achieves 9%-32% reduction in power network area, compared with the results from modern commercial PG synthesizer.
Hierarchical Power Network Synthesis for Multiple Power Domain Designs
(2012)
Lee, Chieh-Jui
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Liu, Sean Shih-Ying
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Huang, Chuan-Chia
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Chen, Hung-Ming
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Lin, Chang-Tzu
In this paper, we propose a methodology that synthesize and optimize the power network for design with multiple power domains. An architecture is presented to represent the power network with presence of sleep transistors. The power network is numerically modeled to RC network using Modified Nodal Analysis and solved using Conjugate Gradient Method. Regarding to IR drop effect mitigation, an optimization technique is proposed based on Simulated Annealing that minimize total power stripe area while satisfying a given IR drop constraint. In consideration of multiple power domains, the given power domains are represented in tree-like structure and our algorithm is recursively applied to synthesize and optimize the power network for each power domain in a hierarchical fashion. The proposed methodology is integrated to commercial design tool and experimented on real design case for evaluation. To ensure practical aspect of our approach, evaluation is performed on latest digital design commercial tool. Design data and parameters are extracted using Open Access. The result of our algorithm is fed back to latest commercial tool for final IR and EM analysis. Our algorithm is tested on both industrial testcase and academic MCNC benchmark. Comparing to conventional P/G network, using our power network synthesis can achieve 31% - 35% reduction in total P/G area while satisfying maximum 10% IR-drop constraint.
I-LUTSim: An Iterative Look-Up Table Based Thermal Simulator for 3-D ICs
(2013-01-01)
Pan, Chi-Wen
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Lee, Yu-Min
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Huang, Pei-Yu
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Yang, Chi-Ping
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Lin, Chang-Tzu
This work presents an iterative look-up table based thermal simulator, I-LUTSim, to efficiently estimate the temperature profile of three-dimensional integrated circuits. I-LUTSim includes two stages. First, the pre-process stage constructs thermal impulse response tables. Then, the simulation stage iteratively calculates the temperature profile via the table lookup. With this two-stage scheme, the maximum absolute error of I-LUTSim is less than 0.41% compared with that of a commercial tool ANSYS. Moreover, I-LUTSim is at least an order of magnitude faster than a fast matrix solver SuperLU [1] for the full-chip temperature simulation.
Improving Power Delivery Network Design by Practical Methodologies
(2014-01-01)
Huang, Chia-Chi
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Lin, Chang-Tzu
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Liao, Wei-Syun
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Lee, Chieh-Jui
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Chen, Hung-Ming
There are many works on the power network design and prototyping for digital designs, however some usual and practical design concerns are not addressed. In this work, we present a realistic power network design methodology without IR violation certified by state-of-the-art commercial tool. Our work integrates analysis, optimization and synthesis of power network. In particular, we consider thermal effect and power pad\'s positions during the prototyping of power network. A scenario in placement regarding the violation of design rules is considered and resolved by maximum flow algorithm at the same stage. After the synthesis of initial power network, we generate a sensitivity matrix which is correlated with nodal voltage and resistances of net and via in metal layers. Furthermore, a Sequential Linear Programming(SLP) will be applied to adjust the sensitivity matrix iteratively until the IR drop constraint is satisfied. Our work is experimented on a real design in TSMC 65nm LP process, and the result validates our framework that the IR-Drop can be reduced to 2% of supply voltage.
Optimization of laser release process for throughput enhancement of fan-out wafer-level packaging
(2018-01-01)
Lee, Chia-Hsin
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Su, Jay
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Liu, Xiao
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Wu, Qi
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Lin, Jim-Wein
Fan-out wafer-level-packaging (FOWLP) technology has been developed with various advantages, such as smaller form factor, lower cost, and simplified supply chain for heterogeneous integration. There have been several process schemes like chip-first or chip-last FOWLP integration discussed widely in conferences in recent years. One process in all of these process schemes has in common is the use of a temporary carrier for subsequent redistribution layer (RDL) formation, chip stacking and molding processes. Although the separation of a temporary carrier from the reconstituted wafer could be achieved without significant hurdles, there were few studies addressing optimization of carrier separation for throughput enhancement. Thus, this paper is designed to address the needs in optimizing carrier separation process based upon laser ablation technology. Two phases of experiments were designed to select the appropriate laser release layer and define optimal laser settings. The first experiment was used to evaluate correlation of the laser absorption, laser energy, and spot pitch versus completeness of laser ablation. The second experiment included RDL-first FOWLP integration. At first, 300-mm glass carriers (1000 mu m thick) with coefficient of thermal expansion of 8 ppm/degrees C were treated by selected laser release layers. After deposition of 0.05-mu m Ti/0.15 mu m Cu on the glass carrier, passivation of around 8 mu m was coated and patterned by lithography for electroplating Cu interconnections with a density of approximately 10% of the surface area. Subsequently, die bonding, build-up layers, or molding compound were applied on top to form a 200-mu m reconstituted wafer. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 355-nm laser to determine optimal throughput. Experiments to study correlation of laser release layer with laser settings along with a demonstration of full RDL-first FOWLP integration are discussed thoroughly to address the need of throughput enhancement, which could serve as cornerstone for realizing cost-effective RDL-first FOWLP.
Skeletally Diverse Synthesis of Innovative [2,1-c]-1,4-Oxazepine and [1,4]-Quinoxaline Systems
(2015-10-01)
Lee, Chia-Hsin
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Wu, Wen-Chun
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Dangate, Prasad S.
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Shen, Li-Ching
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Chung, Wen-Sheng
An efficient, innovative synthesis of [2,1-c]-1, 4-oxazepine and [1,4]-quinoxaline heterocycles along with the embodied pyrimido-pyrrolo motifs was established. Initially, the pyrrole ring was installed using microwave irradiation through an intramolecular base-catalyzed cyclization between acetyl bromomethyl pyrimidine dione and o-amino phenyl methanol or o-phenylenediamine methyl benzoates. Furthermore, oxazepine, and quinoxaline scaffolds were constructed by an acid-catalyzed condensation with a variety of aldehydes by an unconventional Pictet-Spengler reaction strategy. An important aspect of this work is to build novel heterocyclic ring systems with potential medicinal interest.
SRAM cell current in low leakage design
(2006)
Kwai, Ding-Ming
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Hsiao, Ching-Hua
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Kuo, Chung-Ping
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Chuang, Chi-Hsien
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Hsu, Min-Chung
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby power. Experiments using a 0.25 mu m 2.5V standard CMOS process with and without the additional threshold voltage adjustment implant on a 1Mb test chip demonstrate the effectiveness. A substantial standby power reduction by an order of magnitude is achievable. However, it incurs a wider cell current variation, which is pronounced only at a lower supply voltage. As the supply voltage decreases, the percent deviation from the average value increases. This can be modeled by a simple power-law relationship. The result has important implications in both design and manufacturing of the low leakage SRAM. Comparing with the generic cell current without the additional threshold voltage adjustment, the crossover point of their percent deviations at 2V signifies two separate circuit strategies: operating at 1.5V requires larger sensing margin and operating at 2.5V enjoys better manufacturability. Hence, for the applications requiring low voltage operations, it favors a boosted supply voltage applied to a selected cell during the read access.
Synthesis and inhibitory effects of novel pyrimido-pyrrolo-quinoxalinedione analogues targeting nucleoproteins of influenza A virus H1N1
(2015-09-18)
Lin, Meng-I.
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Su, Bo-Han
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Lee, Chia-Hsin
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Wang, Suz-Ting
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Wu, Wen-Chun
The influenza nucleoprotein (NP) is a single-strand RNA-binding protein and the core of the influenza ribonucleoprotein (RNP) particle that serves many critical functions for influenza replication. NP has been considered as a promising anti-influenza target. A new class of anti-influenza compounds, nudeozin and analogues were reported recently in several laboratories to inhibit the synthesis of influenza macromolecules and prevent the cytoplasmic trafficking of the influenza RNP. In this study, pyrimidopyrrolo-quinoxalinedione (PPQ) analogues as a new class of novel anti-influenza agents are reported. Compound PPQ-581 was identified as a potential anti-influenza lead with EC50 value of 1 mu M for preventing virus-induced cytopathic effects. PPQ produces similar anti-influenza effects as nucleozin does in influenza-infected cells. Treatment with PPQ at the beginning of H1N1 infection inhibited viral protein synthesis, while treatment at later times blocked the RNP nuclear export and the appearance of cytoplasmic RNP aggregation. PPQ resistant H1N1 (WSN) viruses were isolated and found to have a NPS377G mutation. Recombinant WSN carrying the S377G NP is resistant to PPQ in anti-influenza and RNA polymerase assays. The WSN virus with the NPS377G mutation also is devoid of the PPQ-mediated RNP nuclear retention and cytoplasmic aggregation. The NPS377G expressing WSN virus is not resistant to the reported NP inhibitors nucleozin. Similarly, the nucleozin resistant WSN viruses are not resistant to PPQ suggesting that PPQ targets a different site from the nucleozin-binding site. Our results also suggest that NP can be targeted through various binding sites to interrupt the crucial RNP trafficking, resulting in influenza replication inhibition. (C) 2015 Elsevier Masson SAS. All rights reserved.
Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology
(2018-08-01)
Shen, Wen-Wei
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Lin, Yu-Min
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Wu, Sheng-Tsai
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Lee, Chia-Hsin
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Huang, Shin-Yi
In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.