Browsing by Author "Lee, Ho-Pei"

Now showing 1 - 4 of 4

Interface Discrete Trap Induced Variability for Negative Capacitance FinFETs
(2018-01-01)
Lee, Ho-Pei
;
Tseng, Kuei-Yang
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Investigation and Comparison of Design Space for Ultra-Thin-Body GeOI/SOI Negative Capacitance FETs
(2017-01-01)
Lee, Ho-Pei
;
Yu, Chien-Lin
;
You, Wei-Xiang
;
Su, Pin
;
電子工程學系及電子研究所
Suppressed Fin-LER Induced Variability in Negative Capacitance FinFETs
(2017-01-01)
Lee, Ho-Pei
;
Su, Pio
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work investigates the impact of fin-LER on the subthreshold characteristics of the negative-capacitance FinFETs by TCAD atomistic simulation coupled with the Landau-Khalatnikov equation. Our study indicates that the variability for V-T, SS and DIBL can be suppressed by the negative-capacitance feedback mechanism. The ferroelectric layer exhibits larger gate voltage amplification for the device with more severe short channel effect and vice versa, and explains the superior immunity to LER variation for the negative capacitance FinFETs.
Suppressed Fin-LER Induced Variability in Negative Capacitance FinFETs
(2017-10-01)
Lee, Ho-Pei
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This letter investigates the impact of fin lineedge roughness (Fin-LER) on the intrinsic variation of negative capacitanceFinFETs (NC-FinFETs) by TCAD atomistic simulation coupledwith the Landau-Khalatnikovequation. We report a feedback mechanism stemming from the internal voltage amplification inherent in the negative capacitance FET. This feedback mechanism results in the superior immunity to Fin-LER-induced threshold-voltage and subthreshold-swing variations for NC-FinFETs as compared with the FinFET counterparts. This lettermay provide insights for device/circuit designs using negative capacitance FETs.