Browsing by Author "Lee, Pei-Yu"

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DATC RDF: Robust Design Flow Database
(2017-01-01)
Jung, Jinwook
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Lee, Pei-Yu
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Wu, Yan-Shiun
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Darav, Nima Karimpour
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Jiang, Iris Hui-Ru
In this paper, we present DATC Robust Design Flow Database covering the stages from logic synthesis to physical design [1]. Based on this database, design flow and cross-stage optimization research can be conducted via various EDA tools developed from academia.
FastPass: Fast Timing Path Search for Generalized Timing Exception Handling
(2018-01-01)
Lee, Pei-Yu
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Jiang, Iris Hui-Ru
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Chen, Tung-Chieh
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
As design complexity rapidly grows, a modem design contains more complex constraints and has more clock domains. To these stringent timing requirements, a design is iteratively optimized. Along with intensive optimizations, fast timing analysis guiding designers to fix timing violations is desired. Thus far, previous works have focused on either timing exception handling or path search only. Different from them, in this paper, we tackle these two issues together for the urgent need in modem design. We first generalize timing exceptions to model all common timing exceptions and other path-specific timing quantities. Then, we propose a novel timing analysis flow that performs fast path search for generalized timing exception handling. Furthermore, we develop three delicate techniques to achieve fast path search, including local slack bounds, dynamic slack recovering, and slack priority queue. Experimental results show that our model is general, and our flow is promising with high efficiency and scalability.
iTimerC 2.0: Fast Incremental Timing and CPPR Analysis
(2015-01-01)
Lee, Pei-Yu
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Jiang, Iris Hui-Ru
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Li, Cheng-Ruei
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Chiu, Wei-Lun
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Yang, Yu-Ming
To achieve timing closure, performance-driven optimizations are repeatedly performed throughout the modern IC design flow. Along with these optimization operations, how to incrementally update timing information efficiently and accurately becomes a crucial task for fast turnaround time. On the other hand, to avoid wasteful over-optimization, clock path pessimism should be removed during timing analysis. In order to provide prompt timing information without over-pessimism during iterative optimizations, in this paper, we aim at fast incremental timing and CPPR analysis. We present two delicate techniques, lazy evaluation and lazy propagation, to avoid redundant updates. Our experiments are conducted on the benchmark suite released by TAU 2015 timing analysis contest. Experimental results show that our timer delivers the best results in terms of accuracy, runtime, and memory over all participating teams.
iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis
(2018-07-01)
Lee, Pei-Yu
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Jiang, Iris Hui-Ru
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this article, we present compact and accurate timing macro modeling, which is the key to efficient and accurate hierarchical timing analysis. Our goal is to contain only a minimal amount of interface logic in our timing macro model. The main idea is to separate the interface logic into variant and constant timing regions. Then, the variant timing region is reserved for accuracy, while the constant timing region is reduced for compactness. For reducing the constant timing region, we propose anchor pin insertion and deletion by generalizing existing timing graph reduction techniques. Furthermore, we devise a lookup table index selection technique to achieve high model accuracy over the possible operating condition range. Compared with two common models used in industry, extracted timing model and interface logic model, our model has high model accuracy and small model size. Based on the TAU 2016 and 2017 timing macro modeling contest benchmark suites, our results show that our algorithm delivers superior efficiency and accuracy: Hierarchical timing analysis using our model can significantly reduce runtime and memory compared with flat timing analysis on the original design. Moreover, our algorithm outperforms TAU 2016 and 2017 contest winners in model accuracy, model size, model generation performance, and model usage performance.
Optimizing hole-injection in organic electroluminescent devices by modifying CuPc/NPB interface
(2011-09-01)
Jiang, Meng-Dan
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Lee, Pei-Yu
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Chiu, Tien-Lung
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Lin, Hong-Cheu
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Lee, Jiun-Haw
This investigation discusses the performance of an organic light-emitting device (OLED) with ultraviolet (UV) illuminated and remote pulsed Ar plasma (RPAP), treated copper phthalcyanine (CuPc) thin film on an indium tin oxide anode as the hole-blocking layer. UV treatment increased the driving voltage, the current efficiency decreased at the same time due to the poor sticking probability of NPB on the CuPc surface. By contrast, the driving voltage reduction and current efficiency enhancement were achieved at the same time for the OLED with the RPAP treated CuPc. Besides this, in such device, the thickness of CuPc affects seldom the current density-voltage-luminance characteristics. The surface characteristics of these processed CuPc thin films were investigated by using atomic force microscope, contact angle and X-ray photoelectron spectroscopy measurements, which showed the CuPc/, N,N'-bis-(1-naphthyl)-N,N'-dipheny1-1,1'-bipheny1-4,4'-diamine (NPB) interface was crucial to not only the interface energy barrier, but also the following NPB growth, mode. (C) 2011 Elsevier B.V. All rights reserved.
SensingGO - Toward Mobile/Cellular Data Measurement with Social and Rewarding Activities
(2018-01-01)
Lin, Yi-Hao
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Chen, Jyh-Cheng
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Lin, Chih-Yu
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Su, Bo-Yue
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Lee, Pei-Yu
Mobile Crowd Sensing (MCS) is a promising paradigm to collect large-scale network data globally. However, how to motivate people to collect and share data is a challenge. We believe the major reason why many MCS systems are not pervasive is because there are no incentives for people to use them. In this paper, we present SensingGO, a system which encourages people to keep sensing data by integrating incentive mechanisms. The sensed data are then transmitted to our backend server. The data we collected and the source code of SensingGO are open to anyone freely. We also demonstrate the analysis of real mobile data collected from SensingGO.
Timing Macro Modeling for Efficient Hierarchical Timing Analysis
(2018-01-01)
Jiang, Iris Hui-Ru
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Lee, Pei-Yu
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this paper, we discuss timing macro modeling, which is the key to enable efficient and accurate hierarchical timing analysis. We briefly review conventional models and recent research progresses in timing macro modeling. We try to answer the following questions: How can timing macro models be made compact and accurate? How do state-of-the art works maintain model accuracy, model size, model generation performance, and model usage performance? Finally, future research directions on timing macro modeling are identified.
Transportation Type Identification by using Machine Learning Algorithms with Cellular Information
(2019-01-01)
Lin, Yi-Hao
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Chen, Jyh-Cheng
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Lin, Chih-Yu
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Su, Bo-Yue
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Lee, Pei-Yu
It is crucial for future 5G networks to intelligently understand how users move so that the networks can allocate different resources efficiently. In this paper, we try to find practical features to identify four common types of motorized transportations, including High-Speed Rail (HSR), subway, railway, and highway. We propose a system architecture that can provide accurate, real-time, and adaptive solution by using cellular information only. Because we do not use GPS as that in most of the prior studies, we can reduce energy consumption, size of log data, and computational time. Around 500-hour data are collected for performance evaluation. Experimental results confirm the effectiveness of the proposed algorithm, which can improve well-known machine learning algorithms to approximately 98% classification accuracy. The results also show that battery consumption can be reduced about 37%.
Voltage Reduction and Lifetime Elongation of Organic Light-Emitting Diodes Using Photopolymerization for Fluorizated Polyxylylene Hole Injection Layer
(2012-03-01)
Jiang, Meng-Dan
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Chiu, Tien-Lung
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Lee, Pei-Yu
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Yang, Shun-Po
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Lin, Hong-Cheu
This study describes a novel method for manufacturing a hole injection layer of an organic light-emitting diode (OLED), comprising an ultraviolet (UV) reactive Br-fluorocarbon precursor (Br-CF2-C6F4-CF2-Br). The proposed method can be used to form a fluorizated polyxylylene film, demonstrating high repeatability on the anode as the hole injection layer of organic electroluminescent devices to enhance the hole injection, reduce the operating voltage of 1.2 V, and extend the operational lifetime by more than 150 times under a high current density of 125 mA/cm(2). Using a spin-coating process, the remaining precursor can be recycled to prevent wasting materials. UV curing without the solvent-removing process shortens manufacturing time. Hence, fabricating a high performance OLED using a simple, low-cost process is the aim of this study. (C) 2012 The Japan Society of Applied Physics