Browsing by Author "Lee, W"

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Acousto-optical effect induced by ultrasound pulses in a nematic liquid-crystal film
(2001-04-01)
Lee, W
;
Chen, SH
;
光電工程學系
;
Department of Photonics
The reorientation of the director of a homeotropically aligned nematic liquid-crystal film subjected to ultrasound pulses is discussed. The relationship is investigated for the first time, to our knowledge, between the transmitted optical power and the high-frequency (approximately megahertz) pulsed ultrasound intensity. It is evident that there exists a power law governing the ultrasound-intensity-dependent optical transmission. However, the data indicate no existence of a characteristic threshold for the acousto-optical effect. Our results suggest that acoustic streaming, known to be responsible for acousto-optical effects in cw ultrasound experiments, should also play a similarly important role in the case involving a pulsed ultrasound field. (C) 2001 Optical Society of America.
An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature
(2006-03-01)
Lee, W
;
Su, P
;
Chen, HY
;
Chang, CY
;
Su, KW
This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.
Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4
(2005)
Lee, W
;
Su, KW
;
Chiang, CS
;
Liu, S
;
Su, P
Modeling geometry-dependent floating-body effect using body-source built-in potential lowering for SOI circuit simulation
(2005-04-01)
Su, P
;
Lee, W
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a compact silicon-on-insulator (SOI) model to capture the geometry-dependent floating-body effect using the body-source built-in potential lowering approach. This physically accurate model circumvents the modeling challenge imposed by the trend of the coexistence of partial-depletion (PD) and full-depletion (FD) devices in a single SOI chip by considering short-channel, reverse short-channel and reverse narrow-width floating-body effects. The implication on circuit simulation, under the unified Berkeley short-channel IGFET model-silicon-on-insulator (BSIMSOI) framework, has also been addressed. This geometry-dependent body-source built-in potential lowering model will further enhance the device design of scaled SOI complementary metal-oxide-semiconductor (CMOS) below 100 nm.
On the prediction of geometry-dependent floating-body effect in SOI MOSFETs
(2005-07-01)
Su, P
;
Lee, W
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This brief demonstrates that, through the perspective of body-source built-in potential lowering (Delta V-bi), the geometry-dependent floating-body effect in state-of-the-art silicon-on-insulator (SOI) MOS-FETs can be explained and predicted by the geometry dependence of threshold voltage (V-T). The correlation between Delta V-bi and V-T unveiled in this brief is the underlying mechanism responsible for the coexistence of partially depleted and fully depleted devices in a single SOI chip.