Browsing by Author "Lee, Wan-Yu"

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Generic Integer Linear Programming Formulation for 3D IC Partitioning
(2012-11-01)
Lee, Wan-Yu
;
Jiang, Iris Hui-Ru
;
Mei, Tsung-Wan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The success of 3D IC requires novel EDA techniques. Although many EDA techniques exist, this paper focuses on 3D IC partitioning, especially at the architectural level to maximize its benefits. First, logical formulations for 3D IC partitioning problems are derived and then the formulations are transformed into integer linear programs (ILPs). The ILP formulation can minimize the usage of vertical interconnects subject to the footprint and power consumption constraints. The flexibility of ILP formulation can be demonstrated by extending the generic ILP formulation to support designs with multiple supply voltages. This study proposes ILP reduction techniques to speed up the convergence. Experimental results based on the GSRC benchmark show that our approach converges efficiently. Moreover, our approach is flexible and can readily extend to the partitioning problems with variant objectives and constraints, and with different abstraction levels, for example, from the architectural level down to the physical level. This flexibility makes the ILP formulation a superior alternative to 3D IC partitioning problems.
Topology generation and floorplanning for low power application-specific Network-on-Chips
(2008)
Lee, Wan-Yu
;
Jiang, Iris Hui-Ru
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Into the nanometer era, the number of cores and the amount of communication on a chip are rapidly increasing. Network-on-Chip can offer high communication efficiency, especially suitable for nanometer designs. Power and timing of low power application-specific Network-on-Chips dominate the system performance and highly depend on how the network topology connects routers and how many routers are used; area is not tightly constrained and Simply determined by floorplanning. Hence, unlike previous endeavors, we propose a new methodology to perform network topology generation before floorplanning. We handle the most important issues at topology generation and preserve the optimality of topology to floorplanning. Compared with previous work, the results show that we can achieve competitive power consumption, guarantee deadlock-free without unnecessary overhead, and significantly improve runtimes.
VIFI-CMP: Variability-Tolerant Chip-Multiprocessors for Throughput and Power
(2009)
Lee, Wan-Yu
;
Jiang, Iris Hui-Ru
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a new architecture of variability-tolerant chip-multiprocessor. To mitigate the impact of process variability on throughput and power, voltage and frequency islands are introduced into chip-multiprocessors. Thus, voltage island frequency island chip-multiprocessors enable per-core scaling on the supply voltage and operating frequency. It can naturally collaborate with dynamic voltage frequency scaling. The process variations are characterized through an analytical model, and are quantified through Monte Carlo analysis. Compared with the design without process variations, when 70 threads are run on a chip of 70 small cores, our results show throughput degradation is 0.06%, while power reduction is 36.27%.