Topology generation and floorplanning for low power application-specific Network-on-Chips

Abstract

Into the nanometer era, the number of cores and the amount of communication on a chip are rapidly increasing. Network-on-Chip can offer high communication efficiency, especially suitable for nanometer designs. Power and timing of low power application-specific Network-on-Chips dominate the system performance and highly depend on how the network topology connects routers and how many routers are used; area is not tightly constrained and Simply determined by floorplanning. Hence, unlike previous endeavors, we propose a new methodology to perform network topology generation before floorplanning. We handle the most important issues at topology generation and preserve the optimality of topology to floorplanning. Compared with previous work, the results show that we can achieve competitive power consumption, guarantee deadlock-free without unnecessary overhead, and significantly improve runtimes.