Browsing by Author "Lee, YS"

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A GaAs/AlAs wet selective etch process for the gate recess of GaAs power metal-semiconductor field-effect transistors
(2001-01-01)
Chang, EY
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Lai, YL
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Lee, YS
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Chen, SH
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材料科學與工程學系
A highly selective wet chemical etch process for gate recess of the GaAs power metal-semiconductor field effect transistors (MES FETs) was developed. The power MESFETs used in this study were epitaxially grown devices with a 20 Angstrom A1As etch-stop layer for gate recess. The selective etch process using citric acid/potassium citrate/hydrogen peroxide solution was studied. A selectivity better than 3800:1 was achieved for GaAs/A1As layers. This selective etch was applied both to high-power, high-voltage power MESFETs and low-voltage large-periphery power MESFETs. For high-power applications, the 14.7 mm device had a breakdown voltage of 22 V. When tested at 1.88 GHz with a drain bias of 10 V, it provided a maximum output power of 38.8 dBm and a maximum power-added efficiency of 52.5%. For low-voltage applications, the 19.8 mm device was tested under IS-95 code-division multiple access (CDMA) modulation at 1.88 GHz with a drain bias of 3.5 V. Under CDMA modulation, the device showed an output power of 28.03 dBm with an adjacent channel power rejection of -29.6 dBc at 1.25 MHz offset frequency. Both devices also showed excellent uniformity in pinch-off voltages. (C) 2000 The Electrochemical Society. S0013-4651 (00)03-053-6. All rights reserved.
A generalized prediction method for modified memory-based high throughput VLC decoder design
(1999-06-01)
Lee, YS
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Shieh, BJ
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Variable-length code (VLC) is the most popular data-compression technique which has been used in many data-compression standards, such as JPEG, MPEG-2, and H.263, In this paper, we present a new memory-based tree-search algorithm and very large scale integration architecture for VLC decoders which can achieve very high decoding throughput performance. Different coding tables can be implemented by simply changing the contents of the memory without changing the system hardware, The coding table is mapped onto a memory whose space requirement has been minimized by using a new tree data structure and efficient memory-mapping strategy. In addition, we break the recursive dependency of iterative searching operations by predicting method. The proposed algorithm and architecture can predict the searching node and perform parallel operations. As a result, the decoding throughput rate can be enhanced to about three to eight times more than previously announced architecture. The proposed architecture mainly consists of memory modules and simple arithmetic unit. Based on 0.6-mu m single poly triple metal CMOS technology and MPEG-2 VLC table-15, the decoder system achieves average decoding throughput rate of 720 Mbits/s at 3 V and a 100-MHz clock rate.
A high throughput context-based adaptive arithmetic codec for JPEG2000
(2002)
Ong, KK
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Chang, WH
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Tseng, YC
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Lee, YS
;
Lee, CY
In JPEG2000 image compression standard, context-based arithmetic coding is adopted for improving compression rate. Efficient and high throughput codec: design is strongly required for handling high-resolution images. We propose an efficient architecture for context-based adaptive arithmetic coding, which can achieve high throughput performance. Based on parallel leading zeros detection and bit-stuffing handling, symbol can be encoded and decoded within one cycle. Therefore, throughput rate can be increased as high as codec operating frequency. The modified encoding and decoding flows are compatible with JPEG2000 standard. For 0.35u 1P4M CMOS technology, encoding and decoding rate can run up to 200Msymbol/sec and 175Msymbol/sec respectively. They are only cost 6.8K and 9.8K gate count. These high throughput performances can meet high-resolution real time application requirement.
A high throughput low cost context-based adaptive arithmetic codec for multiple standards
(2002)
Ong, KK
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Chang, WH
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Tseng, YC
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Lee, YS
;
Lee, CY
For next generation image compression standard, context-based arithmetic coding is adopted for improving compression rate. Efficient and high throughput codec design is strongly required for handling high-resolution images. We propose an efficient codec architecture for context-based adaptive arithmetic coding, which exhibits low cost, low latency, and high throughput rate. In addition, it can be programmed for supporting multiple standards such as JPEG, JPEG2000, JBIG, and JBIG2 standards. It is exploiting three-pipeline stages architecture. Based on parallel leading zeros detection and bit-stuffing handling, symbol can be encoded and decoded within one cycle. Therefore, throughput rate can be increased as high as codec operating clock rate. For 0.35u 1P4M CMOS technology, both encoding and decoding rate can run up to 185Msymbol/sec. The AC codec only costs 12K gate count and 860um x 860um layout area. These performances can meet high-resolution real time application requirement.
A high throughput variable length decoder with modified memory based architecture
(1998)
Shieh, BJ
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Lee, YS
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Variable-Length Code (VLC) is the most popular data compression technique. Therefore, a high throughput Variable-Length Decoder (VLD) is required in many applications. In this paper, we propose 2 simple modified methods which can increase throughput of memory-based two-bit structure Variable-Length Decoder system [1]*. The additional hardware of modified architecture is some control unit and a little memory space. The overall system still consists of control unit, arithmetic unit and memory. Simulation results show that the decompression rate based on 0.6um CMOS process and MPEG2 coding table-15 can achieve 720M bits/s with 100MHz clock rate.
A high-throughput memory-based VLC decoder with codeword boundary prediction
(2000-12-01)
Shieh, BJ
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Lee, YS
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we present a high-throughput memory-based VLC decoder with codeword boundary prediction, The required information for prediction is added to the proposed branch models, Based on an efficient scheme, these branch models and the Huffman free structure are mapped onto memory modules, Taking the prediction information, the decompression scheme can determine the codeword length before the decoding procedure is completed. Therefore, a parallel-processor architecture can be applied to the VLC decoder to enhance the system performance. With a clock rate of 100 MHz, a dual-processor decoding process can achieve decompression rate up to 72.5 Msymbols/s on the average. Consequently, the proposed VLC decompression scheme meets the requirements of current and advanced multimedia applications.
A new approach of group-based VLC codec system with full table programmability
(2001-02-01)
Shieh, BJ
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Lee, YS
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, the algorithm and architecture of a variable-length-code (VLC) codec system using a new group-based approach and achieving full table programmability are presented. According to the proposed codeword grouping and symbol memory mapping, both group searching and encoding/decoding procedures are completed by applying numerical properties and arithmetic operations to codewords and symbol addresses, By a novel symbol conversion, the memory requirement of the encoding process is reduced and the programmability of codewords and symbols is achieved, For MPEG applications, a 0.6-mum CMOS design that performs concurrent VLC codec processes is shown. This VLSI implementation occupies an area of 5.0 x 4.5 mm(2) with 110 k transistors and satisfies a coding table up to 256-entry 12-bit symbols and 16-bit codewords, In addition, both encoding and decoding throughputs of this design achieve 100 Msymbols/s at a 100-MHz clock rate. Therefore, the proposed VLC codec system is suitable for applications which require high operation throughput, such as HDTV, and simultaneous compression and decompression, such as videoconferencing.
A novel DCT-based bit plane error resilient entropy coding for wireless multimedia communication
(2002)
Lee, YS
;
Yu, CM
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Lee, CY
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交大名義發表
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National Chiao Tung University
A novel fixed bit plane error resilient image coding for wireless multimedia transmission
(2002)
Wei, HK
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Lee, YS
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Shih, YH
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Lee, CY
;
電子工程學系及電子研究所
Variable length code (VLC) is the most popular technique using for DCT-based [1] image compression standards such as JPEG MPEG and H.26x. Unfortunately it is highly sensitive to the channel noise. For wireless multimedia transmission, any error bit will cause serious error propagation and result in large image quality degradation. Moreover, it usually has no retransmission chance for real time applications. As a result, high error resilient image coding scheme is important for wireless applications. We propose a novel DCT-based fixed bit plane error resilient image coding (FBP-ERIC) scheme, which can minimize error propagation effect with low redundancy. The complexity is much less than conventional coding schemes In addition, it has high accurate error detection capability for performing error concealment. Even at 0.1% bit-error-rate, 46.5% of erroneous blocks can be accurately detected. Hence, high image quality (PSNR=32.06dB) can be obtained by applying simple error compensation mechanism.
Bipartite Steinhaus graphs
(1999-09-01)
Lee, YS
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Chang, GJ
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應用數學系
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Department of Applied Mathematics
A Steinhaus matrix is a symmetric 0-1 matrix [a(i,j)](nxn) such that a(i,i) = 0 for 0 less than or equal to i less than or equal to n - 1 and a(i,j) = (a(i-1,j-1) + a(i-1,j)) (mod 2) for 1 less than or equal to i < j less than or equal to n-1. A Steinhaus graph is a graph whose adjacency matrix is a Steinhaus matrix. In this paper, we present a new characterization of bipartite Steinhaus graphs.
Characterizations of bipartite Steinhaus graphs
(1999-03-28)
Chang, GJ
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DasGupta, B
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Dymacek, WM
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Furer, M
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Koerlin, M
We characterize bipartite Steinhaus graphs in three ways by partitioning them into four classes and we describe the color sets for each of these classes. An interesting recursion had previously been given for the number of bipartite Steinhaus graphs and we give two fascinating closed forms for this recursion. Also, we exhibit a lower bound, which is achieved infinitely often, for the number of bipartite Steinhaus graphs. (C) 1999 Elsevier Science B.V. All rights reserved.
Comparison of N-2 and NH3 plasma passivation effects on polycrystalline silicon thin-film transistors
(1998-07-01)
Lee, YS
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Lin, HY
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Lei, TF
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Huang, TY
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Chang, TC
The passivation effects of pure N-2 plasma on polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been studied and compared with those of NH3 plasma. We found that, similar to the recently-proposed NH3 plasma passivation, N-2 plasma passivation can also effectively improve device parameters such as field effect mobility, threshold voltage subthreshold swing, off current, and on/off current ratio. While the improvement of NH3-passivated devices can be attributed to both hydrogen and nitrogen passivation effects, nitrogen passivation alone is mainly responsible for the improvement of N-2-passivated devices. Zn addition, we round that N-2-passivated devices exhibit much better hot-carrier reliability than NH3-passivated devices. The better hot-carrier reliability of N-2-passivated devices can be explained by the formation of strong Si-N bonds which are difficult to break, while effectively eliminating the weaker N-H bonds, which are inevitable in NH3-passivated devices. The results of a Fourier. transform infrared (FTIR) spectrum analysis performed in this study are consistent with this proposition.
Construction of error resilient synchronization codeword for variable-length code in image transmission
(2000)
Lee, YS
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Chang, WS
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Ho, HH
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Lee, CY
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電子工程學系及電子研究所
Variable length code ( VLC ), also called Huffman code [1], is the most popular data compression technique used for image compression and transmission. But, it is vulnerable to loss of synchronization under transmission in a noisy channel. It will result in large drops in video transmission quality. For stopping error propagation, synchronization codeword ( SC ) is mostly used to localize error propagation effect. However, most of the SC cannot tolerate noise errors. We propose an iterative and efficient algorithm to construct error-resilient and variable-length SC for any application defined VLC table. They can be sed for synchronization of packet ( ERVL-SOP ). It can be appended at the end of certain number of symbols to form a packet. Thus, channel noise error can be localized. With using constructed SC as SOP, the result shows that it can achieve high signal-to-noise ratio ( PSNR=26dB ) compared to use normal VLC code as SOP at bit error rate ( BER ) of 10(-3) environment. In addition, the incorrect ERVL-SOP detection rate can be decreased to less than 0.0013% effectively.
Correlation of grain boundary characteristics with electrical properties in ZnO-glass varistors
(1998-02-01)
Lee, YS
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Tseng, TY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Grain boundary glass crystallinity was studied to determine its effect on the electrical properties of ZnO-glass varistors. Si-rich glass at the grain boundary layer transformed into a crystalline zinc silicate phase after heat treatment. However, glass without any SiO2 was not recrystallized and remained amorphous following the same process. Variations in non-ohmic behaviour of the samples with three different glass additives are attributed to their different crystallinity. According to a proposed defect reaction equation, strong pinning of the barrier height was found in ZnO-glass varistors with crystallized glass phase. This would ultimately cause an increase in the alpha values, grain boundary barrier height, a breakdown voltage per grain and device stability. If charged ions such as V-o(.), are present due to the formation of the crystalline intergranular phase, the grain boundary barrier height and device stability would initially be enhanced by increased density of interface states, later decreasing due to the migration of zinc interstitials Zn-i(..) under electrical stress. Furthermore, results of deep-level transient spectroscopy, together with dielectric loss and Auger linescan analyses detected three electron traps: L2 is associated with the energy level of the second ionization of interstitial zinc atoms; and the broadness of the trap L3 is analogous to the energy level of the first ionization of oxygen vacancies; trap L1 has been identified as native defects. (C) 1998 Chapman & Hall.
Effects of spinel phase formation in the calcination process on the characteristics of ZnO-glass varistors
(1997-04-01)
Lee, YS
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Tseng, TY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Ceramic varistors based on ZnO with lead zinc borosilicate glass were prepared in order to study the effects of various calcination processes on the formation of spinel phase during the sintering process, including the effects of different temperatures and soaking times. A ZnO-glass sample was prepared using powder calcined at 600 degrees C for 10 h then sintered at 1250 degrees C for 1 h; this sample possessed the highest non-linear coefficient, breakdown voltage and non-linear resistance as well as the lowest leakage current. The optimum amount of Zn7Sb2O12 spinel phase, formed in the calcination process, that can inhibit ZnO grain growth in the subsequent sintering plays an important role in the grain size distribution and stability of ZnO-glass ceramic varistors. Uniform distribution of the grain size obtained from suitable calcination processes was an important microstructural parameter in achieving a good device stability of ZnO-glass varistors. The dynamic resistance and the non-linear resistance of the ZnO-glass varistor, correlated with the average grain size, were proposed to describe insulating characteristics of the varistor samples. Increases in these two parameters, created by decreasing the grain size, enhances the sample clamping voltage during the surge impact and the sample breakdown voltage.
Effects of spinel phase formation in the calcination process on the characteristics of ZnO-glass varistors
(1997-04-01)
Lee, YS
;
Tseng, TY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Ceramic varistors based on ZnO with lead zinc borosilicate glass were prepared in order to study the effects of various calcination processes on the formation of spinel phase during the sintering process, including the effects of different temperatures and soaking times. A ZnO-glass sample was prepared using powder calcined at 600 degrees C for 10 h then sintered at 1250 degrees C for 1 h; this sample possessed the highest non-linear coefficient, breakdown voltage and non-linear resistance as well as the lowest leakage current. The optimum amount of Zn7Sb2O12 spinel phase, formed in the calcination process, that can inhibit ZnO grain growth in the subsequent sintering plays an important role in the grain size distribution and stability of ZnO-glass ceramic varistors. Uniform distribution of the grain size obtained from suitable calcination processes was an important microstructural parameter in achieving a good device stability of ZnO-glass varistors. The dynamic resistance and the non-linear resistance of the ZnO-glass varistor, correlated with the average grain size, were proposed to describe insulating characteristics of the varistor samples. Increases in these two parameters, created by decreasing the grain size, enhances the sample clamping voltage during the surge impact and the sample breakdown voltage.
Error resilient image coding and smart post-processing error concealment for wireless image transmission
(2002)
Ong, KK
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Lee, YS
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Lee, CY
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交大名義發表
;
National Chiao Tung University
Error-resilient image coding (ERIC) with smart-IDCT error concealment technique for wireless multimedia transmission
(2003-02-01)
Lee, YS
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Ong, KK
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The fields of multimedia and wireless communications have grown rapidly in recent years, leading to a great demand for an image-coding scheme that has both compression and error-resilient capabilities. Because bandwidth is a valuable and limited resource, the compression technique is applied to wireless multimedia communication. However, strong data dependency will be created while the bit-rate reduction is achieved. Transmission errors always results in significant quality degradation. In this paper, an error-resilient image coding for discrete-cosine-transform-based image compression is proposed. It can successfully prevent errors from propagating across image block boundaries with little overhead. Additionally, a. novel Post-processing error concealment. scheme is presented to retain low-frequency information and discard suspicious high-frequency information. Low-resolution information, rather than total corruption, can be obtained during the image-decoding process. Because of low complexity and latency properties, it is very suitable for wireless mobile applications. Simulation results show that good image quality (PSNR = 31.78dB) and a low fraction of corruptive blocks (less than 5%) can be achieved even when the bit error rate is 0.1%.
High performance thin-film transistors with low-high-low band gap engineering
(1998)
Chang, CY
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Lee, YS
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Shih, PS
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Lin, CW
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電子工程學系及電子研究所
A novel high-performance thin-film transistor (TFT) with low-high-low band gap structure is proposed. We propose a novel device structure combined with low-band-gap materials (microcrystalline Si, mu c-Si:H) for the channel region, high-band-gap materials (hydrogenated amorphous silicon, a-Si:H) for the source and drain offset regions, and heavily doped low-bandgap materials (n(+) a-Si:H) for ohmic contact of source and drain electrodes. We found that, as compared to a-Si:H TFT device with conventional inverted-stagger structures, the device with low-band-gap materials in the channel (e.g. mu c-Si:H) which possesses high conductance can effectively improve the film quality of initial growth active layer near the gate insulator interface and the grown layer. Hence the TFT device parameters such as field effect mobility, threshold voltage, subthreshold swing and ON-current have been significantly improved. This proposed novel structure with high-band-gap material is used to prevent the band to band tunneling and alleviate the high OFF-current in conventional mu c-Si:H thin-film transistors. The proposed high performance TFTs with low-high-low band gap structure will have a great impact in application to high resolution thin-film transistor liquid-crystal displays (TFT-LCDs) and active-matrix liquid-crystal displays (AMLCDs).
High-performance low-temperature poly-Si TFTs crystallized by excimer laser irradiation with recessed-channel structure
(2001-06-01)
Lin, CW
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Cheng, LJ
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Lu, YL
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Lee, YS
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Cheng, HC
High-performance low-temperature poly-Si (LTPS) thin-film transistors (TFTs) have been fabricated by excimer laser crystallization (ELC) with recessed-channel (RC) structure, The TFTs made by this method possessed large longitudinal grains in the channel regions, therefore, they exhibited better electrical char acteristics as compared with the conventional ones. The average field-effect mobility above 300 cm(2)/V-s and on/off current ratio higher than 10(9) were achieved in these RC-structure devices, In addition, since grain growth could be artificially controlled by this method, the device electrical characteristics were less sensitive to laser energy density variation, and therefore the uniformity of device performance could be improved.