Browsing by Author "Lee, Yu-Huei"

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0.65V-Input-Voltage 0.6V-Output-Voltage 30ppm/degrees C Low-Dropout Regulator with Embedded Voltage Reference for Low-Power Biomedical Systems
(2014-01-01)
Chen, Wei-Chung
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Su, Yi-Ping
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Lee, Yu-Huei
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Wey, Chin-Long
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Chen, Ke-Horng
94% Performance Improvement by Time-shift Control (TSC) Technique in Cloud Computing Voltage Regulator Module (VRM)
(2013)
Meng, Che-Hao
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Su, Yi-Ping
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Huang, Yu-Ping
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Lee, Yu-Huei
;
Chen, Ke-Horng
the time-shift control (TSC) technique for voltage regulator module (VRM) is proposed to achieve high performance power supply for servers in cloud computing. Four power stages are adopted to provide high current driving capability and low output ripple. Besides, the power request, which includes the number of active phases and voltage identification (VID), is acknowledged by servers for high driving capability during high throughput and high efficiency during standby mode. Furthermore, to equally distribute the current in each phase, the proposed TSC technique improves the current balance performance and solves the stability problem. In the scale-down clouding computing prototype, the efficiency can be kept higher than 90% over a wide load current range of 2 A. Besides, the performance and operating frequency of the servers in stable operation are not limited by the VRM with the TSC.
A 65nm Sub-1V Multi-Stage Low-Dropout (LDO) Regulator Design for SoC Systems
(2010)
Lee, Yu-Huei
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Chen, Ke-Horng
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電控工程研究所
;
Institute of Electrical and Control Engineering
This proposed 65 nm sub-1V multi-stage low-dropout (LDO) regulator aims to integrate of power management for SoC systems. The multi-stage structure can derive the high dc voltage gain from the short-channel core devices to insure the load/line regulation. The inserted flying capacitor used to separate the high-frequency non-dominant poles can increase the system phase margin. Moreover, a dynamic gain adjusting (DGA) mechanism can adjust the dc voltage gain based on the load condition to ensure the LDO operation at ultra light loads. The correct operation under sub-1V condition is achieved with 65 nm low-power core devices. Simulated load transient response shows the voltage recovery time is within 0.6 mu s when load current changes from 50 mu A to 100 mA and vice versa.
A 80V Output Voltage Boost Converter with Low Voltage Ripple for Avalanche Photodiode(APD)
(2011)
Yang, Yao-Yi
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Hsieh, Chun-Yu
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Huang, Tzu-Chi
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Lee, Yu-Huei
;
Wang, Shih-Wei
The Avalanche Photodiodes (APDs) are widely used in a variety of optical application requiring high sensitivity, such as long-distance optical communication and optical distance measurement, because the APDs can detect the low level light. APDs accompanied with the Transimpedance Amplifier (TIA) are utilized on the receiver side in the communication system. The trend of integrating the active optical components faces the challenge of integrating different voltage levels. In general, the operation voltage of TIA is usually 1.8 V or 3.3 V. However, the APD requires a high reverse-biasing voltage of 40 V - 80 V. Therefore, a high conversation-ratio boost converter must be included to provide the high voltage to bias the APD. Besides, output voltage ripple must be minimized to decrease the influence on communication signals. Experimental results show the 80 V output voltage boosted from the input voltage of 2.5 V. The output voltage ripple is 2 mV under the condition of 1 mA load current.
A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With alpha-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control
(2012-04-01)
Huang, Tzu-Chi
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Hsieh, Chun-Yu
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Yang, Yao-Yi
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Lee, Yu-Huei
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Kang, Yu-Chai
Abattery-free nano-power buck converter with a proposed dynamic on/off time (DOOT) control can achieve high conversion efficiency over a wide load range. The DOOT control can predict the on/off time at different input voltages without a power consuming zero current detection (ZCD) circuit, as well as suppress static power in idle periods. To adapt to the fluctuations in a harvesting system, the proposed alpha-calibration scheme guarantees accurate ZCD over process, voltage variation, and temperature (PVT) in the DOOT to improve power conversion efficiency. Furthermore, the adaptive phase lead (APL) mechanism can improve inherent propagation delay attributable to low-power and non-ideal comparator, thus improving load regulation by a maximum of 30 mV. The test chip was implemented in 0.25-mu m CMOS process with a die area of 0.39 mm(2). Experimental results showed 95% peak efficiency, low static power of 217 nW and good load regulation of 0.1 mV/mA, which are suitable for RF energy harvesting applications.
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
(2009)
Lee, Yu-Huei
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Wang, Shih-Jung
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Yang, Yao-Yi
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Zheng, Kuo-Lin
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Chen, Po-Fung
The proposed power management module with 1 V low-voltage PWM controller and dynamic self-biasing mechanism is designed to integrate with ultra-wide band (UWB) system. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Instead of using large external compensation circuit, the compensation enhancement multistage amplifier increases system loop gain and stabilizes the system. Moreover, the proposed self-biasing mechanism enhances the power conversion efficiency by 4 % through the handover technique. The fabricated power management module occupies 0.356 mm(2) silicon in 65nm CMOS. With the excellent line/load transient response and the highest efficiency about 93.5%, the proposed power management has the qualification to be integrated in today's system-on-chip (SoC) applications.
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
(2010-11-01)
Lee, Yu-Huei
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Yang, Yao-Yi
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Wang, Shih-Jung
The proposed power management module with a typical 1.2 V low-voltage PWM (LV-PWM) controller and dynamic voltage scaling (DVS) function is designed using 65 nm technology for integration with the ultra-wide band (UWB) system. The on-chip pre-regulator with a power conditioning circuit can provide a regulated supply voltage to the LV-controller. Moreover, the proposed handover technique can achieve the self-biasing mechanism to further reduce power dissipation. To operate in low voltage, the proposed compensation enhancement multistage amplifier (CEMA) can achieve high loop gain and ensure system stability without using any external compensation component. The fabricated power management module occupies 0.356 mm(2) silicon area with an excellent line/load transient response. Owing to the DVS function, the proposed power management can meet the power requirement in the UWB system and other RF transceiver systems.
A High Efficiency Adaptive Frequency Hopping Controlled 1/3x Step-Down Switch Capacitor DC-DC Converter with Deep-Green Mode Operation
(2012)
Ming, Da-Long
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Lee, Yu-Huei
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Chen, Ke-Horng
;
電控工程研究所
;
Institute of Electrical and Control Engineering
A high efficiency adaptive frequency hopping (AFH) controlled step-down switch capacitor (SC) DC-DC converter with deep-green mode (DGM) operation is proposed for system-on-chip (SoC) applications. To obtain the high power conversion efficiency and the small output voltage ripple over a wide load current range, the proposed driving capability control can modulate the load current driving with the closed-loop operation. The AFH control can dynamically adjust the switching frequency according to the distinct output load conditions, so as to ensure adequate load current supply function as well as output voltage regulation. In addition, the DGM operation can mask the switching clock to reduce power loss at ultra light loads for improving power efficiency. This work is implemented by 40 nm CMOS technology. Simulated results demonstrate that the propped SC converter delivers wide load range from 1mA to 300mA. The power conversion efficiency is achieved over 72 % and the output voltage ripple is guaranteed smaller than 30 mV.
A High Efficiency and Compact Size 65nm Power Management Module with 1.2V Low-Voltage PWM Controller for UWB System Application
(2009)
Lee, Yu-Huei
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Wang, Shih-Jung
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Yang, Yao-Yi
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Zheng, Kuo-Lin
;
Chen, Po-Fung
This 65 nm power management module with 1.2 V low-voltage PWM controller aims to integrate with ultra-wideband (UWB) system to get high efficiency and compact size. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Thus, the voltage variation of battery has less effect on the low-voltage PWM controller. The proposed compensation enhancement multistage amplifier (CEMA) increases system loop gain and stabilizes the system without off-chip compensation circuit. With excellent line/load transient response, the proposed power management has the highest efficiency about 92% and 0.995 mm(2) silicon die area.
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement
(2013-04-01)
Lee, Yu-Huei
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Peng, Shen-Yu
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Chiu, Chao-Chang
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Wu, Alex Chun-Hsien
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Chen, Ke-Horng
A low quiescent current asynchronous digital-LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 mm(2) in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 V/mu s as well as the improved MIPS performance by 5.6 times was achieved.
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System
(2012-11-01)
Lee, Yu-Huei
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Chiu, Chao-Chang
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Peng, Shen-Yu
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Chen, Ke-Horng
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Lin, Ying-Hsi
A 65-nm energy-efficient power management with frequency-based control (FBC) is proposed to achieve the near-optimum dynamic voltage scaling (DVS) in a system-on-chip system. Since DVS and dynamic frequency scaling (DFS) operations are demanded for system processor, control loop of the proposed single-inductor dual-output (SIDO) power module is merged with the frequency-controlled phase-locked loop (PLL) to constitute the operation of hybrid control loop. This means that both DVS and DFS operations can be guaranteed and are not affected by process, supply voltage, and temperature variations. The proposed power management can receive the demand of system processor by hybrid control loop and can help realize the supply voltage with different operation tasks for near-optimum DVS operation. The fabricated chip occupies a 1.12-mm(2) silicon area. Experimental results show that the SIDO power module achieves a peak efficiency of 90% and the highest power reduction of 33% with the proposed near-optimum DVS operation.
A Near-Zero Cross-Regulation Single-Inductor Bipolar-Output (SIBO) Converter with an Active-Energy-Correlation Control for Driving Cholesteric-LCD
(2011)
Lee, Yu-Huei
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Fan, Ming-Yan
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Chen, Wei-Chung
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Chen, Ke-Horng
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Liu, Sheng-Fa
A near-zero cross-regulation (near-zero CR) single-inductor bipolar-output (SIBO) converter with an adaptive-energy correlation (AEC) control is proposed as a compact power management solution for driving cholesteric-LCD (Ch-LCD). The SIBO converter can provide a pair of positive and negative output voltages with only one external inductor for achieving the polarity reversion operation in Ch-LCD to obtain high-quality displays. The proposed AEC control decides energy distribution for bipolar outputs without any cross regulation through the embedded prediction function. The chip fabricated in a 0.25 mu m CMOS process demonstrates near-zero cross-regulation at bipolar outputs with 90% peak power conversion efficiency.
A Photovoltaic System with Analog Maximum Power Point Tracking and Grid-Synchronous Control
(2012)
Huang, Tzu-Chi
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Lee, Yu-Huei
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Du, Ming-Jhe
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Hsieh, Chun-Yu
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Yang, Chih-Yu
A low cost maximum power point tracking (MPPT) technique is proposed in this paper for high power efficiency in photovoltaic systems to track the maximum power point (MPP). Compared to the various studies of the MPPT topologies, the proposed implementation is achieved by monitoring the power slope conditions of solar panels. The post grid-connected DC-AC inverter helps feedback the transformative power for providing AC power. Experiment results demonstrate the rapid tracking operation of MPP and a high tracking effectiveness of 97.3%.
A Power Cloud System (PCS) for High Efficiency and Enhanced Transient Response in SoC
(2013-03-01)
Shih, Chun-Jen
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Chu, Kuan-Yu
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Lee, Yu-Huei
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Chen, Wei-Chung
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Luo, Hsin-Yu
Tradeoff between power efficiency and transient performance usually comes out during the design consideration of a power module. A configurable power supplying implementation named as the power cloud system (PCS) is proposed to handle different load conditions for simultaneously improving the power efficiency and the transient response in order to meet the system-on-chip (SoC) requirements. At heavy loads, the switching regulator takes over the energy delivery scheme in the PCS with the fast transient technique. An auxiliary power unit, which activates hybrid operation in both medium and light loads, can realize the low-dropout (LDO) regulator to provide a supplementary energy immediately in transient duration and be the high-side power switches of the switching regulator to minimize the power loss. Besides, owing to its low quiescent current of an LDO regulator, it can directly operate under the ultralight-load condition. Therefore, the satisfactory power conversion efficiency and the load transient response can be derived over a wide load range, which will certainly meet the power requirement for different operated functions in the SoC. The chip was fabricated by a 0.25-mu m CMOS process, and the experimental results show the improvements of 56% transient dip voltage and 25% transient recovery time in hybrid operation, as well as a peak efficiency of 94%.
A Single-Inductor Bipolar-Output Converter with 5 mV Positive Voltage Ripple for Active Matrix OLED
(2011)
Chen, Wei-Chung
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Chiu, Chao-Chang
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Hsieh, Chun-Yu
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Huang, Tzu-Chi
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Lee, Yu-Huei
This paper proposed a single inductor bipolar outputs (SIBO) switching converter for the active matrix Organic Light-Emitting Diode (AMOLED). The negative voltage is generated by the inverting buck-boost converter, which is regulated by the high signal-to-noise ratio comparator. Moreover, the boost converter is utilized to provide the positive output voltage. The proposed switching converter uses the switch sequential to reduce the positive voltage ripple to about 5 mV with the proportional-integral (PI) compensator to guarantee good line and load-regulation. Simulation results show the positive output voltage is regulated to 5V and the negative output voltage is -7V for driving the AMOLED. When the load current is 25 mA and the ESR is 30m Omega, the output voltage ripples are equal to 5 mV and 11 mV for positive and negative voltages, respectively. Besides, the load and line regulations of positive output voltage are 0.24 mV/mA and 5 mV/V, respectively. The maximum efficiency is 88.5% when the input voltage is 4.5 V and the load current is 50mA
A Single-Inductor Dual-Output Converter with Switchable Digital-or-Analog Low-Dropout Regulator for Ripple Suppression and High Efficiency Operation
(2012)
Lee, Yu-Huei
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Chen, Wei-Chung
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Chiu, Chao-Chang
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Peng, Shen-Yu
;
Chu, Kuan-Yu
a single-inductor dual-output (SIDO) converter with the switchable digital-or-analog (D/A) low-dropout (LDO) regulator achieves an analog dynamic voltage scaling (ADVS) function for ripple suppression and high efficiency in system-on-achip (SoC). The ADVS function helps dynamically adjust the dropout voltage of the switchable D/A LDO regulator with analog operation for ripple suppression according to the load current. On other hand, the switchable D/A LDO regulator activates the digital operation for high efficiency at light loads since the dropout voltage of the LDO regulator can be further reduced. Besides, the bidirectional asynchronous signal pipeline (BASP) can realize the 50nA quiescent current in digital LDO regulator. This chip was fabricated by the 40 nm CMOS process. Experimental results demonstrate the switchable LDO regulator operation with the peak efficiency of 92% and the 7 mV output voltage ripple at 200 mA load because of the ripple suppression. The efficiency can be kept higher than 83% even the load current is 1 mA.
A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique
(2014-03-01)
Chen, Wei-Chung
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Ping, Su-Yi
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Huang, Tzu-Chi
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Lee, Yu-Huei
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Chen, Ke-Horng
Dual dynamic voltage scaling (DVS) techniques employed in single-inductor dual-output (SIDO) converters are used to improve the efficiency of the system-on-a-chip (SoC). One DVS technique for digital circuits is controlled by the SoC processor. This paper presents the analog DVS (ADVS) technique for analog circuits to scale voltage across the power MOSFET of the switchable digital-analog (D/A) low-dropout (LDO) regulator which is the post-regulator cascaded in series with the SIDO converter. The ADVS determines the tradeoff between voltage suppression and efficiency. Furthermore, because of the digital operation of the D/A LDO regulator, the quiescent current is further reduced at light loads while the load current requirement is minimized. In addition, the limitation of the capacitor-free LDO is significantly reduced by a few microamperes. The test chip was fabricated using a 40-nm CMOS process. Experimental results demonstrated switchable D/A LDO regulator operation with peak efficiency at 96.7% in analog operation and a 5-mV output voltage ripple at 120-mA load resulting from the advantage of ripple suppression. The power efficiency could be sustained at a value over 92.57% even when the load current decreased to 1 mu A.
A Wide Load Range and High Efficiency Switched-Capacitor DC-DC Converter With Pseudo-Clock Controlled Load-dependent Frequency
(2014-03-01)
Chen, Wei-Chung
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Ming, Da-Long
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Su, Yi-Ping
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Lee, Yu-Huei
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Chen, Ke-Horng
A high efficiency 3.3V-to-1V switched-capacitor (SC) step-down DC-DC converter with load-dependent frequency control (LFC) and deep-green mode (DGM) operation is proposed for system-on-a-chip (SoC) application. According to output loading current, the LFC technique can immediately and dynamically adjust the switching frequency through the use of pseudo-clock generator (PCG) and lead-lag detector (LLD) circuit to obtain high power conversion efficiency and small output voltage ripple over a wide loading current range. Therefore, adequate loading current supplying function and output voltage regulation can be guaranteed. Moreover, the DGM operation, similar to pulse skipping mode, can mask the switching clock to reduce power loss at ultra-light loads for further improving power efficiency. The test chip fabricated in 55 nm CMOS process demonstrates that the proposed fast transient converter can deliver wide load range from 10 mA to 250 mA with two small flying capacitors (C-F1, C-F2 = 0.1 mu F) and one output capacitor (C-OUT = 1 mu F). The peak conversion efficiency is 89% compared to the ideal value of 91% (3 * V-OUT/V-IN). In other words, the peak normalized efficiency is equal to 98%. The overall normalized efficiency is always kept higher than 90% while the output voltage ripple is guaranteed smaller than 30 mV.
Adaptive Pulse Skipping and Adaptive Compensation Capacitance Techniques in Current-Mode Buck-Boost DC-DC Converters for Fast Transient
(2013-01-01)
Ehrhart, Andreas
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Lin, Moris
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Huang, Yung-Sheng
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Lee, Yu-Huei
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Chen, Ke-Horng
to have a good power management especially for portable devices it is necessary to use the whole battery voltage range (e. g. of Lithium-ion batteries), to provide a fixed output voltage of for example 3V. In this paper a fast transient (FT) current mode buck-boost DC-DC converter with adaptive pulse skipping (APS) and adaptive compensation capacitance (ACC) is proposed. The buck-boost DC-DC converter can work in three different modes, buck, boost and buck-boost. It cannot only use the whole battery range from 2.7V to 4.2V, but also has a good response time with a low voltage undershoot/overshoot at load current variations, due to the APS and the ACC. With the proposed fast transient techniques, improvements could be made in the voltage overshoot/undershoot and the response time. In boost mode, the improvements, in the voltage undershoot and the response time from light-to-heavy load (100mA to 500mA), are 16.7% and 58.8%, respectively. In buck mode, 40% and 49.2% and in buck-boost mode, it is 10% and 63.9%. In case of a load variation from heavy-to-light load (500mA to 100mA), similar results could be reached in every operation mode. The proposed DC-DC buck-boost converter realizes a good power management and a good transient performance to generate a stable supply voltage for portable devices. Its working frequency is 1MHz.
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter
(2012-07-01)
Chou, Wen-Shen
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Huang, Tzu-Chi
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Lee, Yu-Huei
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Yang, Yao-Yi
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Su, Yi-Ping
"This paper proposes a 55 nm CMOS 12-bit current- steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the video DAC can meet several different specifications in the power optimized (PO) mode. Furthermore, for DAC, the proposed 3S method, including finger separating, splitting and shifting, achieves good differential nonlinearity (DNL) performance to 0.78/0.4 least significant bit (LSB) and integral nonlinearity (INL) 1.3/1.0 LSB (with/without SIDO converter) without additional calibration. It also suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power efficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing and 1 MHz input. The proposed intrinsic 12-bit DAC and SIDO converter achieve high definition video DAC performance with the benefit of area and energy efficiency."