A 65nm Sub-1V Multi-Stage Low-Dropout (LDO) Regulator Design for SoC Systems

Abstract

This proposed 65 nm sub-1V multi-stage low-dropout (LDO) regulator aims to integrate of power management for SoC systems. The multi-stage structure can derive the high dc voltage gain from the short-channel core devices to insure the load/line regulation. The inserted flying capacitor used to separate the high-frequency non-dominant poles can increase the system phase margin. Moreover, a dynamic gain adjusting (DGA) mechanism can adjust the dc voltage gain based on the load condition to ensure the LDO operation at ultra light loads. The correct operation under sub-1V condition is achieved with 65 nm low-power core devices. Simulated load transient response shows the voltage recovery time is within 0.6 mu s when load current changes from 50 mu A to 100 mA and vice versa.