Browsing by Author "Lei, Tan-Fu"

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A reliability model for low-temperature polycrystalline silicon thin-film transistors
(2007-05-01)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Lee, Po-Hao
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
We proposed here a reliability model that successfully. introduces both the physical mechanisms of negative bias temperature instability (NBTI) and hot carrier stress (HCS) for p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed model is highly matched with the experimental results, in which the NBTI dominates the device reliability at small negative drain bias while the HCS dominates the degradation at large negative drain bias. In summary, the proposed model provides a comprehensive way to predict the lifetime of the p-channel LTPS TFTs, which is especially necessary for the system-on-panel circuitry design.
A simple Spacer technique to fabricate poly-Si TFTs with 50-nm nanowire channels
(2007-11-01)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Chang, Hong-Ren
;
Chang, Che-Lun
;
Lei, Tan-Fu
In this letter, polycrystalline-silicon thin-film transistors (poly-Si TFTs) with 50-nm nanowire (NW) channels, which are fabricated without advanced photolithography by using a side-wall spacer-formation technique, are proposed for the first time. Because the polygate electrode is perpendicularly across poly-Si NW channels to form a trigatelike structure, the proposed poly-Si NW TFT owns outstanding gate controllability. In summary, a simple and low-cost scheme is proposed to fabricate high-performance poly-Si NW TFT suitable for future display manufacturing and practical applications.
Analysis of negative bias temperature instability in body-tied low-temperature polycrystalline silicon thin-film transistors
(2008-02-01)
Chen, Chih-Yang
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
;
Yeh, Kuan-Lin
Negative bias temperature instability (NBTI) degradation mechanism in body-tied low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) is analyzed by the charge-pumping (CP) technique. The properties of bulk trap states (including interface and grain boundary trap states) are directly characterized from the CP current. The increase of the fixed oxide charges is also extracted, which has not been quantified in previous studies of NBTI degradation in LTPS TFTs. The experimental results confirm that the NBTI degradation in LTPS TFTs is caused by the generation of bulk trap states and oxide trap states.
Analysis of pentacene thin film transistors in different atmospheres
(2005)
Wang, Yu-Wu
;
Cheng, Horng-Long
;
Wang, Yi-Kai
;
Hu, Tang-Hsiang
;
Ho, Jia-Chong
This investigation addresses the electrical properties of pentacene-based thin film transistors in air, dry air and high vacuum. A potential barrier model was applied to explain the gate dependent field effect mobility behavior. The results show the trap density in air higher than that in a vacuum.
Bias temperature instabilities for low-temperature polycrystalline silicon complementary thin-film transistors
(2007)
Chen, Chih-Yang
;
Lee, Jam-Wem
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
The degradation mechanisms of both negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) were studied for low-temperature polycrystalline silicon complementary thin-film transistors. Measurements show that both NBTI and PBTI are highly bias dependent; however, the effect of the temperature is only functional on the NBTI stress. Furthermore, instead of interfacial trap-state generation during the NBTI stress, the PBTI stress passivates the interface trap states. We conclude that the diffusion-controlled electrochemical reactions dominate the NBTI degradation while charge trapping in the gate dielectric controls the PBTI degradation. (c) 2007 The Electrochemical Society.
Cerium oxide nanocrystals for nonvolatile memory applications
(2007-12-24)
Yang, Shao-Ming
;
Chien, Chao-Hsin
;
Huang, Jiun-Jia
;
Lei, Tan-Fu
;
Tsai, Ming-Jinn
The characteristics of silicon-oxide-nitride-oxide-silicon-type memories embedded with cerium oxide nanocrystals were demonstrated. They were fabricated by depositing a thin CeO(2) film on the SiO(2) tunneling layer and subsequently rapid-thermal annealing process. The mean size and aerial density of the CeO(2) nanocrystals embedded in SiO(2) are estimated to be about 8-10 nm and (3-7)x10(11)/cm(-2) after a high-temperature annealing with different ambients on 900 degrees C. The program/erase behaviors and data retention characteristics were described to demonstrate its advantages for nonvolatile memory device applications. (c) 2007 American Institute of Physics.
CF4-plasma-induced fluorine passivation effects on poly-Si TFTs with high-kappa Pr2O3 gate dielectric
(2008)
Chang, Chia-Wen
;
Huang, Po-Wei
;
Deng, Chih-Kang
;
Huang, Jiun-Jia
;
Chang, Hong-Ren
High-performance polycrystalline silicon thin-film transistors (poly-Si TFTs) integrating high-kappa Pr2O3 gate dielectric and fluorine-passivated poly-Si film are demonstrated. High gate capacitance density and thin equivalent-oxide thickness provided by the high-kappa Pr2O3 gate dielectric have the advantage of increasing the driving current capability of the TFT device, but an undesirable off-state leakage current could be introduced from the high electric field near the drain side. Introducing fluorine atoms into poly-Si films by employing a low-temperature CF4 plasma treatment can effectively passivate the trap states. With 10 W CF4 plasma treatment on poly-Si film, the electrical characteristics of poly-Si Pr2O3 TFTs can be significantly improved, including a steeper subthreshold swing, smaller threshold voltage, higher field-effect mobility, and better on/off current ratio compared with that without CF4 plasma treatment. The maximum off-state leakage current of the fluorine-passivated TFT is more than one order of magnitude lower than that of the control TFT. Furthermore, the incorporation of fluorine atoms by CF4 plasma treatment also improves the reliability of poly-Si Pr2O3 TFTs against hot carrier stressing, which is due to the formation of stronger Si-F bonds in place of weak Si-H bonds in the poly-Si channel and at the Pr2O3 gate dielectric/poly-Si interface. Therefore, high-performance and high-reliability poly-Si TFTs with Pr2O3 gate dielectric and CF4 plasma treatment on poly-Si film are suitable for active-matrix liquid crystal display application. (c) 2007 The Electrochemical Society.
Channel Film Thickness Effect of Low-Temperature Polycrystalline-Silicon Thin-Film Transistors
(2011-04-01)
Ma, William Cheng-Yu
;
Chiang, Tsung-Yu
;
Yeh, Chi-Ruei
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this paper, the channel-film-thickness effect of low-temperature polycrystalline-Si thin-film transistors (LTPS-TFTs) is investigated. Greater channel film thickness can provide a higher field-effect mobility mu FE, rising from 14.33 to 22.33 cm(2)/V . s, as the channel film thickness increases from 55 to 120 nm, due to grain-size effect. In addition, varying the channel film thickness of LTPS-TFTs results in different junction leakage current due to the source/drain (S/D) junction area effect. Moreover, the S/D series resistance also significantly increases when the channel film thickness is reduced from 120 to 35 nm, leading to poor field-effect mobility mu FE and driving current. Consequently, the optimum channel film thickness for active-matrix liquid-crystal displays may be identified.
Characteristics of HfO(2)/Poly-Si Interfacial Layer on CMOS LTPS-TFTs With HfO(2) Gate Dielectric and O(2) Plasma Surface Treatment
(2008-12-01)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this paper, high-performance complementary-metal-oxide-semiconductor low-temperature polycrystalline-silicon thin-film transistors (CMOS LTPS-TFTs) with HfO(2) gate dielectric are fabricated on one wafer for the first time. Low threshold voltage and excellent subthreshold swing can be achieved simultaneously for N- and P-channel LTPS-TFTs without hydrogenation. In addition, the impacts of the HfO(2)/poly-Si interfacial layer on N- and P-channel LTPS-TFTs are also specified. In order to enhance the characteristics of HfO(2) LTPS-TFT further, oxygen plasma surface treatment is employed to improve the interface quality and passivate the defects of channel grain boundaries, thus increasing the carrier mobility and reducing the phonon scattering. The CMOS LTPS-TFTs with HfO(2) gate dielectric and oxygen plasma treatment would be suitable for the application of system-on-panel.
Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-kappa gate dielectric
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are well investigated for the first time. Under room temperature stress condition, the PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for HfO2 LTPS-TFT. In addition, an abnormal behavior of the I-min degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the HfO2 gate dielectric and the poly-Si grain boundaries.
Characteristics of Pr2O3 gate dielectric thin-film transistors fabricated on fluorine-ion-implanted polysilicon films
(2007)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Huang, Jiun-Jia
;
Chang, Hong-Ren
;
Lei, Tan-Fu
A simple and effective scheme for fabricating high dielectric constant (high-kappa) praseodymium oxide (Pr2O3) gate dielectric thin-film transistors (Pr2O3 TFT) on fluorine-ion-implanted polysilicon films was proposed and demonstrated for the first time. Incorporating the fluorine-incorporation method with high-kappa Pr2O3 gate dielectric cannot only effectively passivate the trap states in the poly-Si film but also significantly increase the gate capacitance density. With the incorporation of fluorine ions, the electrical characteristics of Pr2O3 TFT can be remarkably improved, including smaller threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower gate-induced drain leakage current, and better on/off current ratio. In addition, the incorporation of fluorine ions in the poly-Si film also improves the reliability of Pr2O3 TFT against hot-carrier stress, which is attributed to the formation of stronger Si-F bonds. Therefore, the proposed scheme is a promising technology for high-performance solid-phase crystallized poly-Si TFTs. (c) 2007 The Electrochemical Society. All rights reserved.
Characteristics of self-aligned Si/Ge T-gate poly-Si thin-film transistors with high ON/OFF current ratio
(2007-05-01)
Kuo, Po-Yi
;
Chao, Tien-Sheng
;
Hsieh, Pei-Shan
;
Lei, Tan-Fu
;
電子物理學系
In this paper, we have successfully developed and fabricated self-aligned Si/Ge T-gate poly-Si thin-film transistors (Si/Ge T-gate TFTs) with a thick gate oxide at the gate edges near the source and drain for the first time. The Si/Ge T-gate was formed by selective wet etching of Ge gate layer. The thick gate oxide layer at the gate edges and passivation oxide layer were deposited simultaneously in passivation process. The thick gate oxide at the gate edges effectively reduces the drain vertical and lateral electric fields without additional mask, lightly doped drain, spacer, or subgate bias. The Si/Ge T-gate TFTs not only,reduce the OFF-state leakage current but also maintain a high ON-state current. Experimental results show that the Si/Ge T-gate TFTs have low OFF-state leakage currents, improved ON/OFF current ratio, and more saturated output characteristics compared with conventional TFTs.
Characterization of Highly Strained nFET Device Performance and Channel Mobility with SMT
(2010)
Lu, Chih-Cheng
;
Huang, Jiun-Jia
;
Luo, Wun-Cheng
;
Hou, Tuo-Hung
;
Lei, Tan-Fu
This paper compares and analyzes the strained negative channel field effect transistor (nFET) device performance and the channel mobility behavior obtained by the stress memorization technique (SMT) using two different types of nitride films. These nitride film properties and wafer bowing during SMT fabrication are investigated. The electrical properties of SMT strained nFET devices including current-voltage characteristics, transconductance, carrier mobility, and interface state (D(it)) are also analyzed. Although SMT nitride strain can enhance electron mobility, it is critical to control the nitride properties and its hydrogen content to minimize electron mobility degradation due to interface-state generation. Thus, a simple view of the essential physics of mobility enhancement in SMT strained nFETs has been provided. Results in this work also provide guidance to further nFET performance enhancement in the ever-more challenging device targets of future technology generations. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3416923] All rights reserved.
Characterizing fluorine-ion implant effects on poly-Si thin-film transistors with Pr2O3 gate dielectric
(2008-06-01)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Wu, Shih-Chieh
;
Huang, Jiun-Jia
;
Chang, Hong-Ren
The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k. Pr2O3 as gate dielectric is investigated for the first time. Using the Pr2O3 gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr2O3/poly-Si interface to improve the device electrical properties. The Pr2O3 TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr2O3 TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr2O3 TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr2O3 TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.
Dynamic negative bias temperature instability in low-temperature poly-Si thin-film transistors
(2007)
Chen, Chih-Yang
;
Wang, Tong-Yi
;
Ma, Ming-Wen
;
Chen, Wei-Cheng
;
Lin, Hsiao-Yi
Dynamic negative bias temperature instability in p-channel low-temperature poly-Si thin-film transistors was studied in this paper. The degradation of the devices was found to be voltage and temperature dependent. In addition, the frequency and duty ratio of the gate pulse affects the degree of the device degradation. The mechanism of the device degradation was investigated, and a physical model is proposed to explain the mechanism.
Effect of chemical mechanical polish process on low-temperature poly-SiGe thin-film transistors
(2006)
Shieh, Ming-Shan
;
Chen, Chih-Yang
;
Hsu, Yuan-Jiun
;
Wang, Shen-De
;
Lei, Tan-Fu
The improvement of polycrystalline silicon germanium thin-film transistors (poly-SiGe TFTs) using NH(3) passivation and chemical mechanical polishing (CMP) process was examined. Experimental results indicated that NH(3) passivation could effectively improve the turn on characteristics. Moreover, the TFTs fabricated on polished poly-SiGe film exhibit: higher carrier mobility, better subthreshold swing, lower threshold voltage, and higher on/off current ratio due to the smooth poly-SiGe interface.
Electrical Characteristics of High Performance SPC and MILC p-Channel LTPS-TFT with High-kappa Gate Dielectric
(2009)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Yeh, Chi-Ruei
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this article, high performance p-channel, low temperature polysilicon thin-film transistors (LTPS-TFTs) are fabricated by using HfO(2) gate dielectric and two crystallization methods, solid phase crystallization (SPC) and metal-induced lateral crystallization (MILC) are compared. High field-effect mobility mu(FE) 114 and 215 cm(2)/V s), ultralow subthreshold swing (SS similar to 145 and 107 mV/decade), and low threshold voltage (V(th) similar to -1.05 and -0.75 V) are derived from SPC- and MILC-TFTs with HfO(2) gate dielectric, respectively. These excellent electrical characteristics are due to low trap states and much higher gate capacitance density with equivalent oxide thickness similar to 12.3 nm, resulting in lower operation voltage within 2 V of LTPS-TFT without any passivation method. The comparison of SPC and MILC p-channel LTPS-TFTs with HfO(2) gate dielectric is demonstrated. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3177277] All rights reserved.
Electrical enhancement of poly-Si TFTs using FSG ILD passivation
(2007)
Huang, Jiun-Jia
;
Chang, Chia-Wen
;
Dneg, Chih-Kang
;
Lei, Tan-Fu
;
電子工程學系及電子研究所
Polycrystalline silicon thin-film transistors (poly-Si TFTs) with fluorinated silicate glass (FSG) inter-layer dielectric (ILD) passivation layer were proposed in this study. The outdiffused fluorine atoms from FSG ILD could replace Si dangling bonds at grain boundaries in poly-Si film. The proposed short-channel poly-Si TFTs with FSG ILD passivation have electrical enhancement, including on current, off current, and kink effect, compared to those with undoped SiO2 ILD passivation.
Electrical enhancement of polycrystalline silicon thin-film transistors using fluorinated silicate glass passivation layer
(2008-02-01)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Huang, Jiun-Jia
;
Wang, Tong-Yi
;
Lei, Tan-Fu
Polycrystalline silicon thin-film transistors (poly-Si TFTs) with a fluorinated silicate glass (FSG) passivation layer are proposed and demonstrated in this study. Experimental results reveal that the electrical characteristics can be improved by the incorporation of appropriate amounts of fluorine in the poly-Si film. The poly-Si TFTs with a FSG passivation layer show a high on-current, a low off-state gate-induced drain leakage (GIDL) current, a high field-effect mobility, and a suppressed kink effect, compared with the poly-Si TFTs with an undoped SiO(2) passivation layer. The presence of incorporated fluorine atoms from the FSG passivation layer in the poly-Si channel film can passivate the trap states at the grain boundaries. Furthermore, the incorporation of fluorine atoms can form stronger Si-F bonds near the source and drain sides to enhance the immunity against hot-carrier stress. In addition, the proposed poly-Si TFTs are easy to fabricate, have a low production cost, and are realized using a process compatible with modern TFT manufacturing technology.
Enhanced performance and reliability for solid phase crystallized poly-Si TFTs with argon ion implantation
(2007)
Chang, Chia-Wen
;
Chang, Che-Lun
;
Luo, Wun-Chen
;
Lee, Jam-Wem
;
Lei, Tan-Fu
Performance and reliability improvement for polycrystalline silicon thin-film transistors (poly-Si TFrs) with Argon ion implantation are proposed for the first time. By adopting this novel surface -nucleation solid -phase-cry stallization scheme, not only the grain size of poly-Si can be increased but also the intragranular defects can be suppressed effectively. Therefore, a high quality of poly-Si film in channel with better crystallinity is formed. Argon-implanted TFrs have been successfully fabricated and the experimental results demonstrate a superior field-effect mobility of 46. 06 cm(2)/VS, a fewer grain boundary trap density of 3.44 x 10(12) cm(-2) than those of conventional TFrs. The novel proposed structure is a very promising candidate for the future high-performance large-area device applications.