Browsing by Author "Leu, LY"

Now showing 1 - 12 of 12

A macro model of silicon spiral inductor
(2002-05-01)
Su, CY
;
Chen, LP
;
Chang, SJ
;
Tseng, BM
;
Lin, DC
A new automatic parameter extraction method for modeling Of silicon Spiral inductors is presented. The Concepts on self-resonance frequency (f(sr)) and quality factor of a spiral inductor are utilized to develop the concise extraction procedures. In the mean time, the presented extraction procedures are programmed as a macro to execute all the extractions automatically and shorten the extraction time effectively. Without any additional optimization or curve fitting, almost all the patterns of S-parameters between the measured and the simulation of extracted data implemented with the extraction macro are less than 5%. The programmed extraction macro makes it fast and accurate to extract and characterize the behaviours or silicon-based spiral inductors with different structures and substrate resistivities. It provides a concrete foundation commercial silicon radiofrequency (RF) Circuit design to realizing on-chip silicon RF integrated circuits. Furthermore, the directly extracted equivalent model parameters, without an optimization, also provide a rule to fairly, effectively and phsically judge the performance of a spiral inductor. (C) 2002 Elsevier Science Ltd. All rights reserved.
A study on the radiation hardness of flash cell with horn-shaped floating-gate
(1997-09-01)
Huang, TY
;
Jong, FC
;
Chao, TS
;
Lin, HC
;
Leu, LY
The effects of radiation on the characteristics of split-gate electrical erasable programmable read only memory (EEPROM)/flash cells with recently-proposed horn-shaped floating gates are studied in terms of cell read current; data retention, cycling endurance, program/erase efficiency, threshold voltage and junction leakage. Our results show that the cells appear to survive after 1 Mrad (Si) Co-60 irradiation. Moreover, the after-irradiation cell read current actually increases in the ''erase'' (i.e., low-threshold voltage, high-conducting) state (i.e., improves), albeit the cell read current also increases in the ''program'' (i.e., high-threshold voltage, low-conducting) state (i.e., a degradation). Our results also show that, despite an improvement in the initial read current in the ''erase'' state immediately after radiation, the write/erase cycling endurance of the flash cells is significantly impeded after irradiation, due to a much faster ''window closure'' rate in the ''erase'' state, although the cell read current is found to remain relatively stable in the ''program'' state after cycling.
A study on the radiation hardness of flash cell with horn-shaped floating-gate
(1997-09-01)
Huang, TY
;
Jong, FC
;
Chao, TS
;
Lin, HC
;
Leu, LY
The effects of radiation on the characteristics of split-gate electrical erasable programmable read only memory (EEPROM)/flash cells with recently-proposed horn-shaped floating gates are studied in terms of cell read current; data retention, cycling endurance, program/erase efficiency, threshold voltage and junction leakage. Our results show that the cells appear to survive after 1 Mrad (Si) Co-60 irradiation. Moreover, the after-irradiation cell read current actually increases in the ''erase'' (i.e., low-threshold voltage, high-conducting) state (i.e., improves), albeit the cell read current also increases in the ''program'' (i.e., high-threshold voltage, low-conducting) state (i.e., a degradation). Our results also show that, despite an improvement in the initial read current in the ''erase'' state immediately after radiation, the write/erase cycling endurance of the flash cells is significantly impeded after irradiation, due to a much faster ''window closure'' rate in the ''erase'' state, although the cell read current is found to remain relatively stable in the ''program'' state after cycling.
Characterization and Modeling of on-chip inductor substrate coupling effect
(2002)
Chao, CJ
;
Wong, SC
;
Hsu, CJ
;
Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.
Characterization and modeling of on-chip inductor substrate coupling effect
(2002)
Chao, CJ
;
Wong, SC
;
Hsu, CJ
;
Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.
Characterization and Modeling of on-chip inductor substrate coupling effect
(2002-01-01)
Chao, CJ
;
Wong, SC
;
Hsu, CJ
;
Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.
Characterization and Modeling of on-chip spiral inductors for Si RFICs
(2002-02-01)
Chao, CJ
;
Wong, SC
;
Kao, CH
;
Chen, MJ
;
Leu, LY
The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.
Design optimization of ESD protection and latchup prevention for a serial I/O IC
(2004-02-01)
Huang, CY
;
Chen, WF
;
Chuan, SY
;
Chiu, FC
;
Tseng, JC
ESD/latchup are often two contradicting variables during IC reliability development. Trade-off between the two must be properly adjusted to realize ESD/latchup robustness of IC products. A case study on SERIAL Input/Output (I/O) IC's is reported here to reveal this ESD/latchup optimization issue. SERIAL I/O IC features a special clamping property to wake up PC's during system standby situation. Along with high voltage operation, Input/Output (I/O) protection design of this IC becomes one of the most challenging tasks in the product reliability development. In the initial development phase, ignorance of latchup susceptibility resulted in severe Electrical Overstress (EOS) damage during latchup tests, and also gave a false over estimate of ESD protection threshold through parasitic latchup paths. The latchup origin is an output PMOS and floating-well ESD triggering NMOS beside the PMOS, and the main fatal link is this high-voltage (HV) NMOS connecting to a bi-directional SCR cell. This fatal link led to totally five latchup sites and three latchup paths clarified through careful and intensive FIB failure analysis, while this powerful SCR ESD device without appropriate triggering mechanism still could not provide sufficient product-level ESD hardness. Owing to there being no design window between ESD and latchup, the original several protection schemes were all abandoned. Using this bi-directional SCR ESD cell and proper triggering PNP bipolar transistors, a new I/O protection circuit could sustain at least ESD/HBM 4 kV and latchup triggering current 150 mA tests, thus accomplish the best optimization of ESD/latchup robustness. (C) 2003 Elsevier Ltd. All rights reserved.
Effect of coplanar probe pad design on noise figures of 0.35 mu m MOSFETs
(2000-07-20)
Su, CY
;
Chen, LP
;
Chang, SJ
;
Huang, GW
;
Ho, YP
The effects of different coplanar ground-signal-ground (GSG) probe pads on the noise figure characteristics of submicron MOSFETs are presented. Devices with top-level metal as probe pads shielded by grounded bottom-level metal possess the most appropriate probe pad structure for characterising the noise performance of MOSFETs. Equivalent circuits of the probe pads are used to explain the different noise behaviours.
Effects of floating-gate doping concentration on flash cell performance
(1997-08-01)
Huang, TY
;
Jong, FC
;
Lin, HC
;
Chao, TS
;
Leu, LY
In this paper we report the effects on flash cell performance of the doping concentration of the horn-shaped floating-gate. It is demonstrated that the Boating-gate doping concentration not only determines the work function of the floating-gate, but also affects the resultant interpoly oxide. As a result, the Bash cell performance is affected by the Boating-gate doping concentration, and should therefore be carefully designed. It is shown that a low doping level (e.g., <1.7x10(18) cm(-3)) on the Boating-gate results in a high threshold voltage of the flash cell, low cell read current, and degraded write/erase cycling endurance. Flash cells with a medium (e.g., 1.7 x 10(19) cm(-3)) doping level, on the other hand, depict the lowest threshold voltage, and the highest cell read current; while Bash cells with the highest doping level (1.7x10(20) cm(-3)) used in this study depict a medium threshold voltage. This could be ascribed to the fact that both medium and high doping levels result in a degenerate polysilicon floating-gate with a similar work function; however, a higher doping concentration results in a thicker interpoly oxide, and therefore a higher threshold voltage, and lower read current.
Improved flash cell performance by N2O annealing of interpoly oxide
(1997-07-01)
Jong, FC
;
Huang, TY
;
Chao, TS
;
Lin, HC
;
Leu, LY
In this letter, we report the effects of N2O annealing of interpoly oxide on flash cell performance. It is demonstrated that by adding an N2O anneal after interpoly oxide formation, improved cycling endurance is achieved, The program and erase efficiencies are also improved significantly, compared to the control cell without N2O anneal. The cells with N2O anneal show higher cell current (i.e., drain current), which can be ascribed to a lower threshold voltage and higher transconductance, compared to the control cell.
Improving radiation hardness of EEPROM/flash cell by N2O annealing
(1998-07-01)
Huang, TY
;
Jong, FC
;
Chao, TS
;
Lin, HC
;
Leu, LY
The effects of an N2O anneal on the radiation effects of a split-gate electrical erasable programmable read only memory (EEPROM)/flash cell with a recently-proposed horn-shaped floating gate were studied. We have found that although the cells appear to survive 1 Mrad(Si) Co-60 irradiation without data retention failure, the write/erase cycling endurance was severely impeded after irradiation. Specifically, the write/erase cycling endurance was degraded to 20 K from the pre-irradiation value of 50 K, However, by adding an N2O annealing step after the interpoly oxidation, the after-irradiation write/erase cycling endurance of the resultant cell can be significantly improved to over 45 K, N2O annealing also improves the after-irradiation program and erase efficiencies. The N2O annealing step therefore presents a potential method for enhancing the robustness of the horn-shaped floating-gate EEPROM/flash cells for radiation-hard applications.