Browsing by Author "Li, Pei-Wen"

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A Film-Profile-Engineered 3-D InGaZnO Inverter Technology With Systematically Tunable Threshold Voltage
(2016-09)
Lyu, Rong-Jhe
;
Lin, Horng-Chih
;
Li, Pei-Wen
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this paper, a new depletion-load metal oxide-based inverter with 3-D structure is realized with film-profile-engineered InGaZnO (IGZO) thin-film transistors (TFTs). The proposed inverter possesses vertically stacked load and drive TFTs whose threshold voltage can be flexibly adjusted into a wide range of -2.3-1 V through merely adjusting the geometric parameters without the necessity of additional processes or masks. The 3-D IGZO inverters constructed through the proposed technology demonstrate full-swing switching with voltage gains up to 19 V/V under an operation voltage of 9 V. The 3-D inverters can not only reduce the footprint but also promote the resistance toward light-induced instability.
A model for predicting the thermal conductivity of SiO2-Ge nanoparticle composites
(2015-01-01)
Kuryliuk, Vasyl
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Nadtochiy, Andriy
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Korotchenkov, Oleg
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Wang, Chin-Chi
;
Li, Pei-Wen
We present a simple theoretical model that predicts the thermal conductivity of SiO2 layers with embedded Ge quantum dots (QDs). Overall, the resulting nanoscale architecture comprising the structural relaxation in the SiO2 matrix, deviation in mass density of the QDs compared to the surrounding matrix and local strains associated with the dots are all likely to enhance phonon scattering and thus reduce the thermal conductivity in these systems. We have found that the conductivity reduction can be predicted by the dot-induced local elastic perturbations in SiO2. Our model is able to explain not only this large reduction but also the magnitude and temperature variation of the thermal conductivity with size and density of the dots. Within the error range, the theoretical calculations of the temperature-dependent thermal conductivity in different samples are in close agreement with the experimental measurements. Including the details of the strain fields in oxidized Si nanostructured layers is therefore essential for a better prediction of the heat pathways in on-chip thermoelectric devices and circuits.
A novel photoresist-based film-profile engineering scheme for fabricating double-gated, recess-channel IGZO thin-film transistors
(2020-04-01)
Huang, Yu-An
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Peng, Kang-Pin
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Meng, Yu-Chiao
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Su, Chun-Jung
;
Li, Pei-Wen
We reported an experimental fabrication of double-gated (DG) thin-film transistor (TFT) with IGZO recess-channel using a designer photoresist-based thin-film profile engineering approach. In this approach, an organic shadow mask of photoresist (PR) was formed over a p(+)-Si wafer that was encapsulated by an oxide layer, The lithographically-patterned PR layer is an effective mask for shadowing reactive species during the subsequent deposition steps of IGZO and Aluminum, enabling the formation of IGZO recess-channel and discrete Al source/drain pads at room temperature. The top-gate or DG configurations with the Si substrate serving as the bottom-gate were investigated. The fabricated DG TFTs show significant; improvements in both I-ON and I-OFF as compared with single-gated TFTs. The proposed process scheme is readily applicable to the back-end-of-line of a chip. This work demonstrates the feasibility of IGZO recess-channel TFTs in various gated configurations, enabling a building block for emerging functional devices for More-than-Moore applications. (C) 2020 The Japan Society of Applied Physics
A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step
(2015-05-19)
Lai, Wei-Ting
;
Yang, Kuo-Ching
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Hsu, Ting-Chia
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Liao, Po-Hsiang
;
George, Thomas
We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our "designer" heterostructure are evidenced by the low interface trap density of as low as 2-4 x 10(11) cm(-2) eV(-1) and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.
Au Nanoparticle Light Scattering Enhanced Responsivity in Pentacene Phototransistor for Deep-UV Light Detection
(2015-11-01)
Yuan, Shuo-Huang
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Pei, Zingway
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Lai, Hsin-Cheng
;
Chen, Chien-Hsun
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Li, Pei-Wen
In this letter, a pentacene thin-film phototransistor (PTFP) with gold nanoparticles (Au-NPs) decoration in bottom-gate structure was demonstrated. With the Au-NPs, this device is capable of scattering the free-space ultra-violet (UV) irradiation into the pentacene film. Therefore, the PTFP with Au-NPs exhibit 4.5-A/W responsivity with V-GS = 0 V at the wavelength of 240 nm. Meanwhile, an ultimate 32.4-A/W responsivity can be achieved with V-GS = -10 V at the wavelength of 240 nm. Such an excellent spectral response suggests PTFP is capable for used in daily and disposable UV status assessment.
Back to the Future: Germanium nanoengineering reemerges as the savior of Si functional devices
(2018-01-01)
Li, Pei-Wen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Since the inception of the first transistors in 1940s, the immense body of work on the Group IV semiconductors Si and Ge has spearheaded spectacular advances in solid-state electronics development culminating in the modem integrated-circuit (IC) technology that has enabled a vast landscape of device applications in logic, memory, and computing. Although initially Si supplanted Ge as the material of choice for MOSFETs, more recently Ge-based devices are breaking new ground for widespread and innovative applications in electronics, photonics, communications, and sensing devices. Si and Ge, their alloys (SixGe1-x) have numerous applications in CMOS technologies that are applicable for low-cost and high-density ICs, as well as for high-speed electronics and cost-effective photonics through bandgap and strain engineering. We have successfully developed a CMOS-compatible fabrication approach to create new classes of exciting photonic (light emitter and photoMOSFETs) and electronic (single-electron transistors (SETs)) devices. We sincerely believe that our discoveries and developments on the exquisite Ge electronic and photonic devices have only scratched the "tip of the iceberg" in terms of the exciting device possibilities for electronic and photonic integrated circuits (EPICs) on Si platforms.
Characterization of carrier dynamics in Ge quantum dots through Ge quantum-dot MOSFETs using pulsed voltage technique
(2015)
Kuo, Ming-Hao
;
Chen, Ho-Chane
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Lai, Wei-Ting
;
Li, Pei-Wen
;
電子工程學系及電子研究所
We demonstrated a novel CMOS approach for the fabrication of high-performance Ge quantum dot (QD) MOSFETs offering great promises as optical switches and transducers for Si-based optical interconnects. Measured photocurrent to dark current ratio (I-ph/I-dark) and photoresponsivities from the Ge QD PT were as high as 272,000 and 1.7 A/W, respectively, under incident power of 20 W at 980 nm illumination. Carrier dynamics in Ge QDs were characterized by applying a depleting voltage pulse to the gate of MOSFET and by time-resolved photoluminescence on Ge QD array.
Characterization of Four-Level Random Telegraph Noise in a Gate-All-Around Poly-Si Nanowire Transistor
(2019-01-01)
Chang, You-Tai
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Li, Pei-Wen
;
Lin, Horng-Chih
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Four-level random-telegraph-noise (RTN) characteristics of a gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistor induced by two discrete traps are studied in this work. By carefully analyzing the RTN, depths of the two traps in the gate oxide can be identified separately. Consistent information is obtained by assessing the probability of transitions between different levels.
Coordinated and Simultaneous Formation of Paired Ge Quantum Dots by Thermal Oxidation of Designer Poly-SiGe Spacer Structures
(2020-01-01)
Chen, Han-Yu
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Peng, Kang-Ping
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George, Thomas
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Lin, Horng-Chih
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Li, Pei-Wen
We report a novel self-organized approach for the controllable placement of paired Ge quantum dots (QDs) along each sidewall edge of poly-Si ridges by simply thermally oxidizing spacer layers of poly-SiGe and Si3N4 that conformally encapsulate the poly-Si ridges. Additionally, controllable diameters ranging from 20-50 nm and precise location of paired Ge QDs are enabled by adjusting the thickness of poly-SiGe spacer layers in combination with specific processing conditions. These conditions include the subsequent lithographic patterning through direct etch-back for forming spacer stripes and spacer islands. The spacing between paired Ge QDs across the ridge is essentially determined by the width of the patterned poly-Si ridge. Inter-QD spacings along the sidewall of the poly-Si ridge are a consequence of heterogeneous nucleation and Ostwald Ripening.
Counter-intuitive Ge/Si/O interactions and Ge/Si symbiosis enable the creatation of new classes of exciting nanoelectronic and nanophotonic devices
(2017-01-01)
Hsueh, C. Y.
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Huang, T. L.
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Peng, K. P.
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Kuo, M. H.
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Lin, H. C.
We have successfully exploited multi-dimensional spaces of concentrations of the interstitial species, Si and Ge, geometries and compositions of the starting SiGe nano-pillar, and sources of Si interstitials (the Si3N4 and Si encapsulation layers) to create new classes of exciting optical and electronic devices such as single-electron tunneling devices, wavelength tunable photodetectors, and MOSFETs.
Design of multifold Ge/Si/Ge composite quantum-dot heterostructures for visible to near-infrared photodetection
(2015-05-15)
Kuo, Ming-Hao
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Lai, Wei-Ting
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Lee, Sheng-Wei
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Chen, Yen-Chun
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Chang, Chia-Wei
We demonstrate an effective approach to grow high-quality thin film (>1 mu m) ofmultifold Ge/Si/Ge composite quantum dots ( CQDs) stacked heterostructures for near infrared photodetection and optical interconnect applications. An otherwise random, self-assembly of variable-fold Ge/Si CQDs has been grown on Si through the insertion of Si spacer layers to produce micron-scale-thick, stacked Ge/Si CQD layers with desired QD morphology and composition distribution. The high crystalline quality of these multifold Ge CQD heterostructures is evidenced by low dark current density of 3.68 pA/mu m(2), superior photoresponsivity of 267 and 220 mA/W under 850 and 980 nm illumination, respectively, and very fast temporal response time of 0.24 ns measured on the Ge/Si CQD photodetectors. (C) 2015 Optical Society of America
Designer Ge Quantum-Dot Phototransistors for highly-integrated, broadband optical interconnects
(2016)
Kuo, Ming-Hao
;
Chien, Chung-Yen
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Liao, Po-Hsiang
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Lai, Wei-Ting
;
Li, Pei-Wen
We report high-responsivity Ge quantum dots (QDs) MOS phototransistors as on-chip transducers for highly-integrated, broadband Si-based optical interconnects. Self-organized heterostructure of Ge-QD/SiO2/Si-channel is fabricated in a single step through selective oxidation of SiGe nano-pillars over a Si3N4 buffer layer on Si substrates. Dark current densities (10(-7)A/mm(2)), photocurrent-to-dark current ratio (similar to 10(7)) and photoresponsivities (>10 A/W), external quantum efficiency (similar to 240%), and response time (1.4ns) are measured on the Ge-QD phototransistors under 850 nm illumination. Detection wavelength is tunable from near infrared to near ultraviolet by reducing the QD size from 90 to 7 nm, and the optimal photoresponsivity is tailored by the QD size and effective thickness of gate dielectrics.
Downscaling Metal-Oxide Thin-Film Transistors to Sub-50 nm in an Exquisite Film-Profile Engineering Approach
(2017-03)
Lyu, Rong-Jhe
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Shie, Bo-Shiuan
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Lin, Horng-Chih
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Li, Pei-Wen
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Huang, Tiao-Yuan
We report an exquisite, film- profileengineering approach for producing nanometer-scale channel-length (L) ZnO thin-film transistors (TFTs). The scheme is based on a unique laminated structure in conjunction with a well-designed etching process for building a slender, suspending bridge that shadows the subsequent deposition of pivotal thin films of ZnO and gate oxide as well as simultaneously defines L of the TFTs. With the approach, we have ingeniously downscaled L of ZnO TFTs to as short as 10 nm. The experimental ZnO TFTs of L = 50 and 30 nm, respectively, exhibit excellent performance in terms of high on/off current ratio of 7.9x10(7) and 4.2x10(7), superior subthreshold swing of 92 and 95 mV/decade, and small drain induced barrier lowering of 0.1 and 0.29 V/V. Remarkably the nanometerscale ZnO TFTs possess excellent device uniformity. Furthermore, the precise control over the geometrical sizes for the channel length enables the fabrication of ultrashort ZnO TFTs of L as short as 10 nm with reasonable gate transfer characteristics.
Enhancing the Seebeck effect in Ge/Si through the combination of interfacial design features
(2019-11-08)
Nadtochiy, Andriy
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Kuryliuk, Vasyl
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Strelchuk, Viktor
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Korotchenkov, Oleg
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Li, Pei-Wen
Due to their inherent physical properties, thin-film Si/SiGe heterostructures have specific thermal management applications in advanced integrated circuits and this in turn is essential not only to prevent a high local temperature and overheat inside the circuit, but also generate electricity through the Seebeck effect. Here, we were able to enhance the Seebeck effect in the germanium composite quantum dots (CQDs) embedded in silicon by increasing the number of thin silicon layers inside the dot (multi-fold CQD material). The Seebeck effect in the CQD structures and multi-layer boron atomic layer-doped SiGe epitaxial films was studied experimentally at temperatures in the range from 50 to 300 K and detailed calculations for the Seebeck coefficient employing different scattering mechanisms were made. Our results show that the Seebeck coefficient is enhanced up to approximate to 40% in a 3-fold CQD material with respect to 2-fold Ge/Si CQDs. This enhancement was precisely modeled by taking into account the scattering of phonons by inner boundaries and the carrier filtering by the CQD inclusions. Our model is also able to reproduce the observed temperature dependence of the Seebeck coefficient in the B atomic layer-doped SiGe fairly well. We expect that the phonon scattering techniques developed here could significantly improve the thermoelectric performance of Ge/Si materials through further optimization of the layer stacks inside the quantum dot and of the dopant concentrations.
Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel
(2018-04-01)
Chang, You-Tai
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Peng, Kang-Ping
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Li, Pei-Wen
;
Lin, Horng-Chih
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電機學院
In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core. (C) 2018 The Japan Society of Applied Physics.
Fabrication and RTN Characteristics of Gate-All-Around Poly-Si Junctionless Nanowire Transistors
(2016)
Yang, Chen-Chen
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Chen, Yung-Chen
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Lin, Horng-Chih
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Chang, Ruey-Dar
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Li, Pei-Wen
Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (Gm). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition.
Feasibility of Ge double quantum dots with high symmetry and tunability in size and inter-dot spacing
(2019-01-01)
Peng, Kang-Ping
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Huang, Tsung-Lin
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George, Thomas
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Lin, Horng-Chih
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Li, Pei-Wen
We report the tunability of the sizes and inter-dot spacings of Ge coupled quantum dots (QDs) using nano-spacer technology in combination with selective oxidation of Si0.85Ge0.15. Spherical-shaped Ge QDs were formed at each sidewall corner of the nano-patterned Si3N4 ridges by thermal oxidation of poly-SiGe spacer layers encapsulating the Si3N4 nano-ridges. The diameters of the Ge spherical QDs are essentially determined by geometrical height, width, and length of the nano-spacer islands of poly-SiGe, which are tunable by adjusting the process times of their deposition and etch back. The inter-dot spacing between the Ge DQDs are controllable by adjusting the widths of the lithographically-patterned Si3N4 ridges and the thermal oxidation times. Our self-organization and self-alignment approach achieved high symmetry within the Ge DQDs in terms of the individual QD sizes as well as the coupling barriers between the QDs and external electrodes in close proximity.
Film-Profile-Engineered IGZO Thin-Film Transistors with Gate/Drain Offset for High Voltage Operation
(2016)
Wu, Ming-Hung
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Lin, Horng-Chih
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Li, Pei-Wen
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Huang, Tiao-Yuan
;
電機學院
IGZO transistors with various gate/drain-offset lengths (L-GDO) were fabricated with the film-profile-engineering method. Breakdown voltage (V-BD) of the fabricated devices increases while transconductance (gm) decreases with increasing LGDO. In contrast, threshold voltage and subthreshold swing remain relatively unchanged. VBD of similar to 80 V is obtained with LGDO of 0.3 mu m . Output characteristics with operation voltage up to 50 V are also demonstrated, evidencing the capability of the device for high-voltage operation. Impact of hot-carrier stress is also investigated in this work.
Film-profile-engineered ZnO thin-film transistor with gate/drain offset for high-voltage operation
(2019-06-01)
Wu, Ming-Hung
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Lin, Horng-Chih
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Li, Pei-Wen
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We report the design and fabrication of ZnO thin-film transistors (TFTs) configured with designed gate-to-drain (G/D)-offset structures and an auxiliary gate (AG) in a film-profile engineering (FPE) approach for back-end-of-line high-voltage (HV) operation. The breakdown voltage (V-BD) of fabricated FPE TFTs is significantly enhanced from 23 to 90 V by changing the G/D-offset length from -0.3 to 0.5 mu m, whereas there is a corresponding decrease in the on-state current and transconductance (G(m)). To boost the on-state current, an AG biased in the range of 0-5 V is designed to effectively modulate the resistivity of the G/D-offset region and improve G(m) by a factor of 2 while keeping V-BD of 65-70 V nearly unchanged. Output characteristics with drain voltage as high as 60 V have been demonstrated, evidencing the promising potential of the ZnO TFTs for HV device applications. (C) 2019 The Japan Society of Applied Physics
Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devices
(2015)
Lai, Wei-Ting
;
Yang, Kuo-Ching
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Liao, Po-Hsiang
;
George, Thomas
;
Li, Pei-Wen
We reported a first-of-its-kind, self-aligned gate-stack heterostructure of Ge-nanoshpere-gate/SiO2/SiGechannel on Si in a single-step approach through selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on Si substrate. Good tunability on the Ge-nanoshpere size, SiO2 thickness, and SiGe-shell thickness provides a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices with size-tunable Ge gates, SiO2 gate oxide, and SiGe channels. Detailed interfacial morphologies and structural properties between the Ge nanosphere/SiO2 and SiO2/SiGe-channel were examined using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Both Al/SiO2/Genanospheres and NiGe/SiO2/SiGe MOS capacitors exhibit quite low interface trap densities of 3-5x10(11) cm(-2)eV(-1), which is beneficial for advanced Ge MOS applications.