Browsing by Author "Liang, Hao-Wen"

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Asymmetric Low Temperature Bonding Structure Using Ultra-thin Buffer Layer Technique for 3D Integration
(2016)
Liang, Hao-Wen
;
Yu, Ting-Yang
;
Chang, Yao-Jen
;
Chen, Kuan-Neng
;
電子工程學系及電子研究所
Wafer-level Sn/In-Cu bonding structure with Ni ultra-thin buffer layer is investigated to achieve a reduction in solder thickness, bonding temperature and duration. Furthermore, the asymmetric bonding structure is able to separate the manufacturing process of solder and electrical isolation layer. It is a promising approach for the application on hybrid bonding of three-dimensional integration.
Study of a Novel Amorphous Silicon Temporary Bonding and Corresponding Laser Assisted De-bonding Technology
(2016)
Huang, Yu-Hsiang
;
Liang, Hao-Wen
;
Cheng, Chuan-An
;
Lin, Chien-Hung
;
Lee, Chia-Lin
A novel amorphous silicon temporary bonding and corresponding laser assisted de-bonding technology are investigated for the improvement of 3D integration. Excellent bonding results with real device wafer with alpha-IGZO thin-film transistor are shown at the bonding temperature of 210 degrees C, as well as outstanding performances for bonding strength, thermal stability, reliability and chemical resistance. Laser ablated amorphous silicon is proved stable and ultra-fast. Advantages of excellent bonding quality, lower cost and higher throughput demonstrate that this scheme can be a potential candidate in 3D integration platform.
The Influence of Device Morphology on Wafer-Level Bonding with Polymer-Coated Layer
(2016-01-01)
Liang, Hao-Wen
;
Chen, Hsiu-Chi
;
Lin, Chien-Hung
;
Lee, Chia-Lin
;
Yang, Shan-Chun
Thetolerance of device morphology in wafer-level bonding through polymer-coated layer was investigated for the application of 3D integration. Several different pillar heights were fabricated on wafers to simulate the case of bonding with real devices on wafers. Overall, the wafer morphology with polymer-coated layer above devices less than 2 mu m can achieve excellent bonding quality. Furthermore, undamaged carrier wafers can be obtained after laser-assisted de-bonding technology, and post clean treatment. Based on bonding results, this research can provide a practical concept on device morphology for polymer-based temporary wafer-level bonding in 3D integration.