Browsing by Author "Liao, Lei"

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Dielectric Engineering of a Boron Nitride/Hafnium Oxide Heterostructure for High-Performance 2D Field Effect Transistors
(2016-03-09)
Zou, Xuming
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Huang, Chun-Wei
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Wang, Lifeng
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Yin, Long-Jing
;
Li, Wenqing
A unique design of a hexagonal boron nitride (h-BN)/HfO2 dielectric heterostructure stack is demonstrated, with few-layer h-BN to alleviate the surface optical phonon scattering, followed by high-kappa HfO2 deposition to suppress Coulombic impurity scattering so that high-performance top-gated two-dimensional semiconductor transistors are achieved. Furthermore, this dielectric stack can also be extended to GaN-based transistors to enhance their performance.
Enhanced Reliability of In-Ga-ZnO Thin-Film Transistors Through Design of Dual Passivation Layers
(2018-07-01)
Abliz, Ablat
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Wan, Da
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Chen, Jui-Yuan
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Xu, Lei
;
He, Jiawei
This paper investigates the effects of different passivation layers (PVLs) on the electrical performance and reliability of amorphous indium gallium zinc oxide (a-In-Ga-ZnO) thin film transistors (TFTs). By rational design, the fabricated a-InGaZnO TFT with hafnium oxide and aluminum oxide (HfO2/Al2O3) dual PVLs exhibits a field-effect mobility of 13.5 cm(2)/Vs, low sub threshold swing of 0.32 V/decade, and especially, small threshold voltage shifts of 0.5 (-0.6) V and 1.1 (-1.2) V under positive (negative) gate bias, and light illumination stress at the relative humidity of 40%. Furthermore, the a-In-Ga-ZnO TFTs with HfO2/Al2O3 dual PVLs maintain reasonable mobility and electrical performance even exposure to ambient condition for up to four months. This enhanced stability is attributed to the presence of high-quality HfO2/Al2O3 dual PVLs, which not only could suppress the photodesorption, reduce the total trap density and subgap photoexcitation behavior, but also protect the channel from environmental effects. Thus, the rational-designed HfO2/Al2O3 dual PVLs passivated a-In-Ga-ZnO TFTs with superior reliability represent a great step toward the achievement of long-term reliable zinc oxide-based oxide TFTs.
High Mobility MoS2 Transistor with Low Schottky Barrier Contact by Using Atomic Thick h-BN as a Tunneling Layer
(2016-10-05)
Wang, Jingli
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Yao, Qian
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Huang, Chun-Wei
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Zou, Xuming
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Liao, Lei
High-performance MoS2 transistors are developed using atomic hexagonal boron nitride as a tunneling layer to reduce the Schottky barrier and achieve low contact resistance between metal and MoS2. Benefiting from the ultrathin tunneling layer within 0.6 nm, the Schottky barrier is significantly reduced from 158 to 31 meV with small tunneling resistance.
High on/off ratio black phosphorus based memristor with ultra-thin phosphorus oxide layer
(2019-11-04)
Wang, Yudan
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Wu, Facai
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Liu, Xingqiang
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Lin, Jun
;
Chen, Jui-Yuan
The scaling down of switching media encounters high leakage current in the traditional oxide material based memristors, resulting in high power consumption of chips. Two-dimensional (2D) materials promise an ultimate device scaling down to atomic layer thickness. Herein, black phosphorus (BP) and its self-assembly phosphorous oxide (BP) memristors are constructed, which leverages the high on/off ratio operation of oxides and low leakage current of 2D materials with high performance. The memristors exhibit reproducible and reliable switching characteristics with the on/off ratio >10(7) and data retention >10(4) s. Depending on the high reproducibility, basic "AND" and "OR" gates have been constructed on flexible substrates. Moreover, on the basis of the symmetry and linearity of conductance in the devices, the neural network simulation for supervised learning presents an online learning accuracy of 91.4%. This work opens an avenue for future flexible electronics.
Interface Engineering for High-Performance Top-Gated MoS2 Field-Effect Transistors
(2014-09-24)
Zou, Xuming
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Wang, Jingli
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Chiu, Chung-Hua
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Wu, Yun
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Xiao, Xiangheng
Experimental evidence of the optimized interface engineering effects in MoS2 transistors is demonstrated. The MoS2/Y2O3/HfO2 stack offers excellent interface control. Results show that HfO2 layer can be scaled down to 9 nm, yet achieving a near-ideal sub-threshold slope (65 mv/dec) and the highest saturation current (526 mu A/mu m) of any MoS2 transistor reported to date.
Interface Engineering via MoS2 Insertion Layer for Improving Resistive Switching of Conductive-Bridging Random Access Memory
(2019-04-01)
Wu, Facai
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Si, Shuyao
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Cao, Peng
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Wei, Wei
;
Zhao, Xiaolong
Conductive-bridging random access memory (CBRAM), dominated by conductive filament (CF) formation/rupture, has received much attention due to its simple structure and outstanding performances for nonvolatile memory, neuromorphic computing, digital logic, and analog circuit. However, the negative-SET behavior can degrade device reliability and parameter uniformity. And large RESET current increases power consumption for memory applications, By inserting 2D material, molybdenum disulfide (MoS2), for interface engineering with the device configuration of Ag/ZrO2/MoS2/Pt, the negative SET behavior is eliminated, and the RESET current is reduced simultaneously. With the ion barrier property of MoS2, the CF can probably not penetrate the MoS2 layer, thus eliminating the negative-SET behavior. And with the low thermal conductivity of MoS2, the internal temperature of the device would be relatively high at RESET, accelerating probably redox reactions. As a result, the RESET current is reduced by an order of magnitude. This interface engineering opens up a way in improving the resistive switching performances of CBRAM, and can be of great benefit to the potential applications of MoS2 in next-generation data storage.
Low Interface Trap Densities and Enhanced Performance of AlGaN/GaNMOS High-Electron Mobility Transistors Using Thermal Oxidized Y2O3 Interlayer
(2015-12-01)
Liao, Chongnan
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Zou, Xuming
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Huang, Chun-Wei
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Wang, Jingli
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Zhang, Kai
AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with Y2O3 interlayer have been investigated to improve the interface quality. With the HfO2/Y2O3 stack gate dielectrics, the devices show a saturated drain current density of up to similar to 943 mA/mm. Meanwhile, the pulsed I-d-V-g measurement indicates interface traps are as low as 5.2 x 10(11) cm(-2), and the pulsed-IV measurement exhibits great resistance to current collapse. Furthermore, the devices also present good reliability under negative bias stress. Therefore, the interface engineering based on Y2O3 has a potential to open up a new avenue to high-performance AlGaN/GaN MOS-HEMTs.
Possible absence of critical thickness and size effect in ultrathin perovskite ferroelectric films
(2017-06-06)
Gao, Peng
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Zhang, Zhangyuan
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Li, Mingqiang
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Ishikawa, Ryo
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Feng, Bin
Although the size effect in ferroelectric thin films has been known for long time, the underlying mechanism is not yet fully understood and whether or not there is a critical thickness below which the ferroelectricity vanishes is still under debate. Here, we directly measure the thickness-dependent polarization in ultrathin PbZr0.2Ti0.8O3 films via quantitative annular bright field imaging. We find that the polarization is significantly suppressed for films <10-unit cells thick (similar to 4 nm). However, approximately the polarization never vanishes. The residual polarization is similar to 16 mu Ccm(-2) (similar to 17%) at 1.5-unit cells (similar to 0.6 nm) thick film on bare SrTiO3 and similar to 22 mu Ccm(-2) at 2-unit cells thick film on SrTiO3 with SrRuO3 electrode. The residual polarization in these ultrathin films is mainly attributed to the robust covalent Pb-O bond. Our atomic study provides new insights into mechanistic understanding of nanoscale ferroelectricity and the size effects.
Rational Design of ZnO:H/ZnO Bilayer Structure for High Performance Thin-Film Transistors
(2016-03-30)
Abliz, Ablat
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Huang, Chun-Wei
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Wang, Jingli
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Xu, Lei
;
Liao, Lei
The intriguing properties of zinc oxide-based semiconductors are being extensively studied as they are attractive alternatives to current silicon-based semiconductors for applications in transparent and flexible electronics. Although they have promising properties, significant improvements on performance and electrical reliability of ZnO-based thin film transistors (TFTs) should be achieved before they can be applied widely in practical applications. This work demonstrates a rational and elegant design of TFT, composed of poly crystalline ZnO:H/ZnO bilayer structure without using other metal elements for doping. The field-effect mobility and gate bias stability of the bilayer structured devices have been improved. In this device structure, the hydrogenated ultrathin ZnO:H active layer (similar to 3 nm) could provide suitable carrier concentration and decrease the interface trap density, while thick pure-ZnO layer could control channel conductance. Based on this novel structure, a high field-effect mobility of 42.6 cm(2) V-1 s(-1), a high on/off current ratio of 108 and a small subthreshold swing of 0.13 V dec(-1) have been achieved. Additionally, the bias stress stability of the bilayer structured devices is enhanced compared to the simple single channel layer ZnO device. These results suggest that the bilayer ZnO:H/ZnO TFTs have a great potential for low-cost thin-film electronics.
The different roles of contact materials between oxidation interlayer and doping effect for high performance ZnO thin film transistors
(2015-02-02)
Xu, Lei
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Huang, Chun-Wei
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Abliz, Ablat
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Hua, Yang
;
Liao, Lei
To improve the performance of ZnO thin film transistors (TFTs) by using appropriate metal contacts, the different roles of contact materials between oxidation interlayer and doping effect are investigated. With careful characterization, an oxidation interlayer has been verified at the interface between ZnO film and Al or Ti contact, which is suggested to be responsible for contact resistance and thermal reliability. On the other hand, it is observed that the doping effect is the main reason for the Sn or Cu contact characteristics. The superior contact using Sn is due to an oxidation-free interface, donor doping effect, and a low barrier height. By using a metal contact with a high Gibbs free energy, the metal layer would hardly consume oxygen from channel layer during sputtering and easily form no oxidation interlayer. Thus, choosing a metal contact is important when fabricating high-performance metal-oxide TFTs for flat-panel displays. (C) 2015 AIP Publishing LLC.