Browsing by Author "Liao, Ming-Han"

Now showing 1 - 4 of 4

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors
(2014-10-20)
Lee, Ya-Ju
;
Yang, Zu-Po
;
Chen, Pin-Guang
;
Hsieh, Yung-An
;
Yao, Yung-Chi
In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication. (C) 2014 Optical Society of America
Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors: reply
(2018-01-22)
Lee, Ya-Ju
;
Yang, Zu-Po
;
Chen, Pin-Guang
;
Hsieh, Yung-An
;
Yao, Yung-Chi
We present some comments to the paper "Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors: comment" [Opt. Express 22, A1589 (2014)]. (C) 2017 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack
(2016-04-01)
Liu, Chien
;
Chen, Ping-Guang
;
Xie, Meng-Jie
;
Liu, Shao-Nong
;
Lee, Jun-Wei
The concept of ferroelectric (FE) negative capacitance (NC) may be a turning point in overcoming the physical limitations imposed by the Boltzmann tyranny to realize next-generation state-of-the-art devices. Both the body factor (m-factor) and the transport mechanism (n-factor) are simultaneously improved by integrating an NC with a tunnel FET (TFET). The modeling approach is discussed in this study as well as the NC physics. By optimizing the thicknesses of FE, semiconductor, and interfacial layers, the capacitance of the FE layers is modulated to match that of a MOS resulting in the smallest subthreshold swing that is also hysteresis-free. An ultrathin-body double gate tunnel FET (UTB-DG-TFET) exhibits a steep slope (a subthreshold swing below 10 mV/dec over more than 4 orders of magnitude) for low-power applications (<0.2V switching voltage) to realize next-generation state-of-the-art devices. (C) 2016 The Japan Society of Applied Physics
Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack
(2016-04)
Liu, Chien
;
Chen, Ping-Guang
;
Xie, Meng-Jie
;
Liu, Shao-Nong
;
Lee, Jun-Wei
The concept of ferroelectric (FE) negative capacitance (NC) may be a turning point in overcoming the physical limitations imposed by the Boltzmann tyranny to realize next-generation state-of-the-art devices. Both the body factor (m-factor) and the transport mechanism (n-factor) are simultaneously improved by integrating an NC with a tunnel FET (TFET). The modeling approach is discussed in this study as well as the NC physics. By optimizing the thicknesses of FE, semiconductor, and interfacial layers, the capacitance of the FE layers is modulated to match that of a MOS resulting in the smallest subthreshold swing that is also hysteresis-free. An ultrathin-body double gate tunnel FET (UTB-DG-TFET) exhibits a steep slope (a subthreshold swing below 10 mV/dec over more than 4 orders of magnitude) for low-power applications (<0.2V switching voltage) to realize next-generation state-of-the-art devices. (C) 2016 The Japan Society of Applied Physics