Browsing by Author "Liao, Yu-Te"

Now showing 1 - 20 of 42

A 0.8V, 43.5 mu W ECG Signal Acquisition IC with a Referenceless Time-to-Digital Converter
(2016)
Lin, Shu-Hsuan
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Lin, Fu-To
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Cheng, Nai-Chen
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Liao, Yu-Te
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電機工程學系
This paper presents a 0.8V analog front-end (AFE) with referenceless time-based digitalization architecture for electrocardiogram (ECG) signal acquisition. Compared to the conventional voltage-domain architecture, the proposed AFE achieves a smaller chip area, lower power consumption, and self-calibration without the high-accuracy clock as well as voltage reference. The chip is fabricated using 0.18 mu m CMOS technology and occupies a chip area of 0.84 mm(2). The design attains a variable gain from 35 dB to 47 dB within a bandwidth of 7 kHz and 10-bit time-to-digital conversion while consuming 43.5 mu W at a supply voltage of 0.8V.
A 145 mu W 315MHz Harmonically Injection-Locked RF Transmitter with Two-Step Frequency Multiplication Techniques
(2017-01-01)
Dau, Nan
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Chen, Yen-Ting
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Liao, Yu-Te
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a low-power RF transmitter with harmonic injection locking and capacitive-coupling frequency multiplication techniques. To save power, the design operates at a low frequency except for the RF Class-E power amplifier. The chip, which was fabricated using 0.18 um CMOS technology, has an area of 0.49 mm X 0.93 mm. The proposed model can achieve a maximum transmission power of -21.3 dBm, data rate of 2 Mbps, and energy efficiency of 0.071nJ/bit while consuming 145 mu W.
A 2.2 mu W,-12 dBm RF-Powered Wireless Current Sensing Readout Interface IC With Injection-Locking Clock Generation
(2016-07)
Lin, Fu-To
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Lu, Shao-Yung
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Liao, Yu-Te
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電機學院
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College of Electrical and Computer Engineering
This paper presents a wireless-powering current-sensing readout system on a CMOS platform for portable electrochemical measurement. The wireless sensing system includes energy-efficient power management circuitry, a sensor readout interface, and a backscattering wireless communication scheme. For power-and-area-constrained bio-sensing applications, the proposed readout circuitry incorporates an ultra-low-power potentiostatic system that generates a current according to the electrochemical reaction, as well as an oscillator-based time-to-digital converter instead of a voltage-domain analog-to-digital converter. To avoid a bulky battery and power-hungry clock reference, the chip is wirelessly powered and injection-locked by the modulated radio waves, which includes a 918 MHz carrier signal mixed with a 3.2 MHz modulated signal. The chip, implemented using a 0.18-mu m CMOS process, occupies a silicon area of 1 mm(2). The proposed design achieves a sensitivity of 289 Hz/nA and an R-2 linearity of 0.997 over a current range of 200 nA while consuming 2.2 mu W at a supply voltage of 0.8 V. The chip, integrated with a PCB antenna, has minimum sensitivities of -12 dBm and -25 dBm for RF-powering and injection-locking mechanisms, respectively.
A 2.4 GHz Low Phase Noise In-Phase Coupled Class-C Quadrature VCO in 0.18 mu m CMOS
(2015-10-01)
Wu, Chuan-Yi
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Liao, Yu-Te
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
This letter presents a 2.4 GHz Class-C QVCO using an in-phase coupling topology. The phase noise of the proposed QVCO is effectively reduced by using a lower gate biasing voltage at the cross-coupled pairs and an in-phase coupling technique. A complementary Class-C oscillator is employed to enhance the startup robustness over a temperature range from -25 degrees C to 100 degrees C. A quadrature oscillator, implemented in a 0.18 mu m CMOS process, achieves a phase noise lower than -130.7 dBc/Hz at 1 MHz offsets and a frequency tuning range from 2.23 to 2.57 GHz while only consuming 3 mW. The design attains a remarkable figure-of-merit of 193.7 dBc/Hz.
A 2.6mW,-192dB/Hz FOM Class-C QVCO Using Capacitive Source Degeneration Coupling
(2014-01-01)
Hong, Zhi-Hao
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Wu, Chuan-Yi
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Liao, Yu-Te
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
The paper presents a novel Class-C type QVCO using a capacitive source coupling mechanism to enhance the startup robustness over process-temperature-voltage variations. Class-C type oscillator has superior phase noise performance with low power consumption at the cost of weak startup. In this design, complementary architecture and capacitive source degeneration coupling are employed to increase the loop gain of Class-C quadrature oscillator. The capacitive coupling mechanism also provides extra phase shifts that eliminate the quality factor degradation of the LC tank in QVCO design. An optimal coupling factor is derived to compromise power-phase noise trade-offs. The proposed 2.4GHz QVCO, fabricated in 0.18 mu m CMOS technology, achieves -128dBc/Hz at 1MHz offsets while only consuming 2.6mW. The design attains a remarkable figure-of-merit (FOM) of -192dB/Hz.
A 45 mu W, 9.5MHz Current-Reused RC Oscillator Using a Swing-Boosting Technique
(2017-01-01)
Lu, Shao-Yung
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Liao, Yu-Te
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資訊工程學系
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Department of Computer Science
This paper presents a differential relaxation oscillator that uses swing-boost and current-reused techniques. Output swing boosting is adopted to improve noise performance, and current-reused architecture reduces the power consumption of the oscillator. Since oscillation frequency is defined by the resistor and capacitor, combining opposite temperature coefficient resistors helps eliminate temperature-caused frequency drifts. The proposed RC oscillator is fabricated using 0.18 mu m standard CMOS technology. The design achieves an FOM of 161.5 dBc/Hz with a phase noise of -108.5 dBc/Hz at 100kHz offset and an Allan deviation floor of 5.2 ppm at a 2-second integral window while consuming 45 mu W. The measured temperature coefficient is 307 ppm/degrees C in the temperature range of -20-100 degrees C, and the measured period jitter is 10.5 ps(rms).
A 46 mu W, 8.2MHz Self-threshold-tracking Differential Relaxation Oscillator with 7.66psrms Period Jitter and 1.56ppm Allan Deviation Floor
(2018-01-01)
Lu, Shao-Yung
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Liao, Yu-Te
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents an 8.2MHz relaxation oscillator with swing boosting and self threshold tracking, designed to improve both period jitter and frequency stability. A self-threshold-tracking loop ensures the switching threshold is kept in a constant, reducing the frequency uncertainty from process, temperature and supply voltage variations. Implemented in a 180nm CMOS process, the design achieves a period jitter of 7.66psrms, an Allan deviation floor of 1.56ppm, a temperature coefficient of 123ppm from-20 to 100 degrees C, and an FOM of 160.9dBc/Hz while only consuming 46.3 mu W. The power efficiency of the design is 5.6kHz/nW.
A 918MHz Wide-Range CMOS Rectifier with Diode-Feeding and Switch-Capacitor-Based Load Modulation Technique
(2019-01-01)
Kuo, Chen-Yi
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Lu, Chun-An
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Liao, Yu-Te
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交大名義發表
;
National Chiao Tung University
This paper presents a wide-input-range rectifier design with a diode-feeding (DF) architecture and load modulation. Dynamically-biased diodes are connected to the gates of the rectifying transistors to create bias voltage differences for PMOS and NMOS devices and the isolation of the reverse currents at different input power levels. Also, the switch-capacitor-based load modulation scheme is proposed to achieve optimal efficiency over wide-range load current deviations automatically. The proposed four-stage rectifier design was fabricated using 65nm CMOS technology and occupies a silicon area of 0.92 x 0.27mm(2). The measured sensitivity of the rectifier is -15dBm at 1M Omega load, and the peak power conversion efficiency is 28% at a load of 22k Omega With the load modulation scheme, the conversion efficiency is enhanced by >10% in a load current from 7 mu A to 35 mu A, when compared to a design without the load modulation scheme.
A Fully-Integrated Wireless Bondwire Accelerometer With Closed-loop Readout Architecture
(2015-10-01)
Liao, Yu-Te
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Huang, Shih-Chieh
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Cheng, Fu-Yuan
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Tsai, Tsung-Heng
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電機資訊學士班
This paper presents a fully-integrated wireless bondwire accelerometer using a closed-loop readout interface that effectively reduces the noise from electrical circuits and long-term frequency drifts. The proposed accelerometer was fabricated using 0.18-mu m CMOS technology without micro electromechanical systems (MEMS) processing. To reduce manufacturing errors, the bondwire inertial sensors are wire-bonded on the chip pads, thereby enabling a precisely-defined length and space between sensing bondwires. The proposed wireless accelerometer using a pair of 15.2 mu m and 25.4 mu m bondwires achieves a linear transducer gain of 33 mV/g, bandwidth of 5 kHz, a noise floor of 700 mu g/root Hz, and 4.5 mu g bias stability. The acceleration data is digitalized by an energy-efficient 10-bit SAR ADC and then wirelessly transmitted in real time to the external reader by a low-power on-off shift keying (OOK) transmitter. The proposed architecture consumes 9 mW and the chip area is 2 mm x 2.4 mm.
A High-Efficiency Power Management IC with Power-Aware Multi-path Rectifier for Wide-Range RF Energy Harvesting
(2017-01-01)
Lin, Shu-Hsuan
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Kuo, Chen-Yi
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Lu, Shao-Yung
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Liao, Yu-Te
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電機工程學系
A highly-integrated CMOS power-management system with wide-range RF for ultra-high frequency (UHF) wireless energy harvesting is presented. To avoid environment-caused sudden power loss and to scavenge energy efficiently, the proposed power management system adopts power-aware rectifier architecture and adaptive DC-DC conversion ratios according to the input power level. The proposed system was fabricated in a 0.18-mu m CMOS process. The system achieved a peak RF/DC conversion efficiency of 59%, a sensitivity of -11.6dBm, and a 13.5dB RF input range for at least 20% power efficiency at a 100K Omega load. At the high input power region (>-9dBm), the proposed architecture improves about 15% efficiency when compared to a conventional rectifier followed by a linear regulator. The peak efficiency of the entire system is 37%.
A Low Power 2.4/5.2GHz Concurrent Receiver Using Current-Reused Architecture
(2016)
Hsu, Hung-Sheng
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Duan, Qiu-Yue
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Liao, Yu-Te
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a low-power 2.4/5.2GHz concurrent receiver for emerging wireless sensing applications. The RF front-end design includes a concurrent dual-band low noise amplifier (LNA), a stacked mixer and VCO architecture, and variable-gain baseband amplifiers (VGA). Current-reused techniques, by sharing gain stages and stacked components, are explored in the receiver design for the further reduction of power consumption. The prototype chip, which was fabricated in a 0.18 mu m CMOS process, occupies a chip area of 3.67mm(2), including pads and impedance matching networks. At the 2.4GHz band, the proposed receiver achieves a maximum gain of 43dB, a noise figure of 8.9dB, and a 1-dB compression point (P1dB) larger than -34dBm. At the 5.2GHz band, the proposed receiver achieves a maximum gain of 31dB, a noise figure of 16.3dB, and a P1dB larger than -27dBm. The total power consumption is 7.3mW at a supply voltage of 1.2V.
A Low-Power Wireless Bondwire Inertial Sensor System
(2015)
Huang, Shih-Chieh
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Lu, Shao-Yung
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Cheng, Fu-Yuan
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Tsai, Tsung-Heng
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Liao, Yu-Te
This paper presents the design and implementation of a fully-integrated CMOS accelerometer using bondwires as sensing devices without Micro Electro-Mechanical Systems (MEMS) processes. The model and analysis of bondwire inertial sensors are provided for further implementation of low-power and low-noise accelerometers. Finite element method (FEM) simulation is performed to verify the concept and model. This paper also proposes a closed-loop readout interface that suppresses the in-band noise and reduces both design complexity and power consumption. The bondwire accelerometer is fabricated in a 0.18 mu m CMOS process, achieves a 33 mV/g linear transducer gain within a 5 kHz bandwidth, and consumes 9 mW.
A Low-Power, Differential Relaxation Oscillator With the Self-Threshold-Tracking and Swing-Boosting Techniques in 0.18-mu m CMOS
(2019-02-01)
Lu, Shao-Yung
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Liao, Yu-Te
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a fully integrated, 8.2-MHz relaxation oscillator with a self-threshold-tracking loop and swing-boosting technique for improving its long-term frequency stability and noise performance. The proposed latch-based relaxation oscillator increases the transition speed to reduce the static power consumption. To decrease the process-voltagetemperature dependence, we propose a self-threshold-tracking loop to ensure that the transition point of the inverter-based comparator is set to a fixed ratio of the supply voltage. In addition, the comparator delay can be compensated by the tracking loop, relaxing the requirements of comparator power consumption. The design is implemented in a 0.18-mu m CMOS process. The design achieves a period jitter of 7.66 psrms, the phase noise of -109 dBc/Hz at an offset frequency of 100 kHz, and an Allan deviation noise floor of 1.56 ppm. The resultant figure of merit is 160.8 dBc/Hz, while only consuming 46.3 mu W. The power efficiency of the design is 5.6 kHz/nW. As for the supply sensitivity, the design achieves 0.9 %/0.1 V, which is 10x lower than the design with no compensation loop. The measured temperature coefficient of the proposed oscillators is 123 ppm/degrees C from -20 degrees C to 100 degrees C without any trimming process.
A Microwatt Dual-Mode Electrochemical Sensing Current Readout With Current-Reducer Ramp Waveform Generation
(2019-12-01)
Chen, Yi-Chia
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Lu, Shao-Yung
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Liao, Yu-Te
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電機工程學系
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Department of Electrical and Computer Engineering
An electrochemical sensing chip with an integrated current-reducer pattern generator and a current-mirror based low-noise chopper-stabilization potentiostat circuit is presented. The pattern generator, utilizing the current reducer technique and pseudo resistors, creates a sub-Hz ramp signal for the cyclic voltammetric (CV) measurement without large-size passive components. The proposed design adopts the chopper-stabilization and low-noise biasing technique for the potentiostat and a counter-based time-to-digital converter to reduce the amplitude noise effects and to convert the sensing current signal to digital codes for further data processing. The design is fabricated using a 0.18-m CMOS process and achieves a 41pA current resolution in the current range of 5A while maintaining the R-2 linearity of 0.998. The system consumes 16W from a 1.2V supply when a 5A sensing current is detected. The power efficiency of the readout interface is 0.31, and the sensing current dynamic range is 108dB. The design is fully integrated into a single chip and is successfully tested in the dual-mode (CA/CV) measurements with commercial gold electrodes in a potassium ferricyanide solution in sub-millimolar concentrations.
A Power-efficient Bidirectional Potentiostat-based Readout IC for Wide-range Electrochemical Sensing
(2018-01-01)
Tsai, Jui-Hsiang
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Chen, Yi-Chia
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Liao, Yu-Te
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a low-power electrochemical sensor readout IC with a bi-directional potentiostat for accommodating a large dynamic sensing current range. The proposed chopper stabilization potentiostat, suppressing low-frequency noise at the front end and providing stable positive and negative potentials between the working and reference electrodes for bi-directional current sensing through a switched push-pull readout stage. The digital implementation of an oscillator-based current to frequency converter and frequency counter transforms the sensing current directly into digital codes. The design is realized in a 0.18 mu m CMOS process and occupies an area of 1.3mm(2), including all passive components and pads. The proposed readout IC achieves a 0.9pA minimum detectable current in a current range of +/- 18 mu A, an R-2 linearity of 0.999, and a dynamic detectable current range of 152dB. The static power consumption of the proposed readout IC is 2.9 mu W from a 1.5V supply.
A Power-efficient, Bi-directional Readout Interface Circuit for Cyclic-voltammetry Electrochemical Sensors
(2019-01-01)
Chen, Yi-Chia
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Lu, Shao-Yung
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Tsai, Jui-Hsiang
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Liao, Yu-Te
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電機工程學系
This paper presents an electrochemical sensing front-end circuit with a cyclic voltammetry potentiostat. To accommodate a large and bidirectional current sensing range for the current-mirror based potentiostat, a constant offset current is added. With the technique of chopper-stabilization, the flicker noise of the readout circuit is successfully reduced. A charge-based oscillator is also proposed in this paper to convert the current into a frequency for further data readout. The proposed readout IC was fabricated in a 0.18 mu m, 1.2V CMOS process and the current range is -2 mu A similar to 12.2 mu A, the R-2 linearity of 0.992, with a minimum detectable current of 3.1nA. The dynamic current range is 73.2dB whereas the chip consumes 40.5 mu W at a maximum sensing current of 12.2 mu A.
A Reconfigurable, Pulse-shaping Potentiometric Readout System for Bio-Sensing Transistors
(2019-01-01)
Lu, Shao-Yung
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Shan, Siang-Sin
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Yang, Jiancheng
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Chang, Chin-Wei
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Ren, Fan
This paper presents a new multi-modality readout system for potentiometric electrochemical sensors. The design adopts a pulse modulation at the gate and drain of the Bio-FET sensors to reduce the effects of charge accumulation between the surface of the electrodes and the ion analytes. The adjustable duration and amplitude of stimuli signals provide flexibility for different biosensing applications and a wide range of detectable concentration. Also, an oscillator-based architecture is proposed for digitization and integration. The counting time can be adjusted to enhance the resolution of the readout system. The proposed potentiometric sensing system was tested with 0.1-10 mM Potassium Ferricyanide (K-3[Fe(CN)(6)]), and the results are interpreted in the micro-LCD on the board. The design offers the opportunity for a handheld medical device with fast and real-time monitoring of biomarkers and ion analytes.
A Self-Powering Wireless Environment Monitoring System Using Soil Energy
(2015-07-01)
Lin, Fu-To
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Kuo, Yu-Chun
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Hsieh, Jen-Chien
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Tsai, Hsi-Yuan
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Liao, Yu-Te
This paper presents a self-powering wireless environment monitoring system using renewable and cost-efficient soil energy. The D-size (55.8 cm(3)) soil energy cell with carbon and zinc electrodes can produce similar to 60-100 mu W, depending on the water contents and microbial reactions in the soil. The RC circuit model of a soil cell is proposed for understanding the electrical characteristics of the cell. The wireless sensing system, including temperature and air moisture sensors, a custom low-power capacitive sensor readout silicon chip, a microcontroller, and a Bluetooth low-energy transmitter, is demonstrated for long-term environmental monitoring solely by the fabricated D-size soil cell. The capacitive sensor readout chip is fabricated in a 0.18-mu m CMOS process and only consumes 3 mu W. The capacitance readout range is 160-200 pF. The total power consumption of the wireless temperature and air moisture monitoring system is similar to 20 mu W and 1 mW in the sleep mode and the active wireless data communication operations, respectively. The new technology can enable remote field environment monitoring with less labor-intensive work and battery replacement.
A Sustainable Soil Energy Harvesting System With Wide-Range Power-Tracking Architecture
(2019-10-01)
Ou, I-Che
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Yang, Jia-Ping
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Liu, Chia-Hung
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Huang, Kai-Jie
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Tsai, Kun-Ju
For wide-range deployment of wireless sensing nodes in power- and size-constrained Internet of Things applications, self-sustaining wireless sensors without batteries are needed. The energy supply for these ubiquitous sensing devices should harness environmental energy sources to avoid frequent battery replacement and pollution. This paper presents a new soil energy harvesting system with a power management integrated circuit (IC) for wide-range maximum power point tracking (MPPT). The output power of a soil energy cell varies widely according to the soil moisture and soil contents. To extract the maximum amount of energy from the soil, high-efficiency power management with adaptive dc-dc conversion ratios and an MPPT mechanism is essential. The proposed system is implemented with a high-efficiency dc-dc converter IC in a 0.18-mu m CMOS process. The design achieves a peak tracking efficiency of 90.5% in the throughput power range from 56 mu W to 1 mW at an output voltage of 3 V and system efficiency exceeding 65% over an input resistance range of the soil energy source; the peak system efficiency is 73.9%. A demonstration was undertaken of the soil energy harvesting system lighting an LED array without any chemical batteries.
A Wide-Range Capacitive DC-DC Converter with 2D-MPPT for Soil/Solar Energy Extraction
(2018-01-01)
Ou, I-Che
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Yang, Jia-Ping
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Liu, Chia-Hung
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Huang, Kai-Jie
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Tsai, Kun-Ju
This paper presents a capacitive DC-DC converter with adaptive DC-DC conversion ratios and maximum power point tracking (MPPT) for soil and solar energy extraction. To overcome the varying input power ranges of the soil/solar energy sources, a two-dimension power tracking loop with time-based current slope detection was employed. The design was fabricated in a 0.18 mu m CMOS process, achieving >80% efficiency in a throughput power range of 360 mu W to 25mW in the soil mode and from 400 mu W to 10mW in the solar mode while the peak system efficiency is 89.5%.