Browsing by Author "Lien, WY"

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0.13 mu m low voltage logic based RF CMOS technology with 115GHz f(T) and 80GHz f(MAX)
(2003)
Guo, JC
;
Huang, CH
;
Chan, KT
;
Lien, WY
;
Wu, CM
Superior RF CMOS of 115GHz f(T) and 80GHz f(max) has been realized by 0.13mum low voltage logic based RF CMOS technology by aggressive device scaling and optimized layout. NFmin of 2.2dB at 10GHz is achieved even without deep N-well and ground-shielded signal pad. P,dB of near 10dBm can fit bluetooth requirement and 55% PAE at 2.4 GHz address the good potential of sub-100nm CMOS for low voltage RF power applications.
0.13-mu m low-kappa-Cu CMOS logic-based technology for 2.1-Gb high data rate read-channel
(2004-05-01)
Guo, JC
;
Lien, WY
;
Tsai, TL
;
Chen, SM
;
Wu, CM
High-performance analog/digital elements have been successfully fabricated bya 0.13-mum low-kappa-Cu logic-based mixed-signal CMOS process in a single chip to enable a 2.1-Gb/s read-channel for hard disk drives that is a record-high data rate supported by fully CMOS solution. The high-performance analog devices demonstrate superior drivability, matching, noise immunity, and reliability by a unique dual-gate oxide module to support the aggressive oxide thickness scaling and maintain promisingly good reliability in all aspects.
0.13-mu m RF CMOS and varactors performance optimization by multiple gate layouts
(2004-12-01)
Ho, CC
;
Kuo, CW
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Chan, Y
;
Lien, WY
;
Guo, JC
0.13-mum radio frequency (RF) CMOS devices with multifinger gate structure have been fabricated by the standard logic process, and the measured effective gate-length is 80 nm. Extensive RF characterization has been done to obtain cutoff frequency (f(T)), associated power gain cutoff frequency (f), minimum noise figure (NFmin), output power (P-out), and power added efficiency (PAE) for RF circuit design and to explore the optimized gate layout in terms of the extracted RF device parameters. Our important finding to be reported in this paper is that an optimized unit finger width (W-F) exists by trade-off among f(T), f(.max), NFmin, P-out, and PAE. Under fixed total width to achieve the same current drivability (I-ds), the smaller W-F and the larger finger number (N-F) leads to higher f(max) but lower f(T) due to trade-off between gate resistance (R-g) and parasitic gate capacitance. As for NFmin complicated by f(T) and R-g, counter-balance between parasitic gate capacitance and R-g leads to nearly constant NFmin. w.r.t. various splits of (W-F, N-F). Regarding P-out and PAE, W-F of 4 mum and NF of 18 is the optimized layout parameter, which offers the maximum P-out of around 11 dBm and PAE of 30.5% at 5.8 GHz. The performances of accumulation-mode MOS varactors with different gate layout structures are also investigated in this report. Since the same area varactors with different gate layout may result in different parasitic resistance and fringing capacitance, which will affect the capacitance tuning range and the associated Q-factor. The maximum Q-factor is about 59 of the 120 mum(2) gate area varactor, and its tuning range is from 210 IF to 1.64 pF, where the maximum C-max/C-min ratio is about 7.8.
A simple transmission line de-embedding method for accurate RF CMOS noise modeling
(2004)
Guo, JC
;
Huang, CH
;
Lien, WY
;
Wu, CM
;
電子工程學系及電子研究所
We propose a simple method to de-embed the transmission line and pads' parasitics from the measured RF noise of multi-finger MOSFETs with aggressive gate length scaling down to 80 nm and 65 nm respectively. Good agreement has been realized between measurement and simulation in terms of S-parameters and NFmin (minimum noise figure) for RF CMOS devices with various finger numbers by using this novel de-embedding method. The extracted NFmin after de-embedding matches well with the published noise correlation matrix method but is relatively simple without resort to complicated matrices calculation.
Pocket implantation effect on drain current flicker noise in analog nMOSFET devices
(2004-08-01)
Wu, JW
;
Cheng, CC
;
Chiu, KL
;
Guo, JC
;
Lien, WY
The pocket implantation effect on drain current flicker noise in 0.13 mum CMOS process based high performance analog nMOSFETs is investigated. Our result shows that pocket implantation will significantly degrade device low-frequency noise primarily because of nonuniform threshold voltage distribution along the channel. An analytical flicker noise model to account for a pocket doping effect is proposed. In our model, the local threshold voltage and the width of the pocket implant region are extracted from the measured reverse short-channel effect, and the oxide trap density is extracted from a long-channel device. Good agreement between our model and the measurement result is obtained without other fitting parameters.