Browsing by Author "Lin, Ching-Shiang"

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Low Power UWB CMOS LNA Using Resistive Feedback and Current-Reused Techniques Under Forward Body Bias
(2017-01-01)
Guo, Jyh-Chyurn
;
Lin, Ching-Shiang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A ultra-wideband (UWB) low noise amplifier (LNA) has been realized in 0.18 mu m CMOS technology. The current-reused method combined with forward body bias (FBB) in a cascade amplifier can enable an aggressive voltages scaling, such as V-DD and V-G1 to 1.0V and 0.53V, i.e. 44.5% and 70.6% reduction compared to the typical VDD of 1.8V. The low voltage feature from FBB leads to more than 50% saving of power dissipation to 5.2mW. The on-chip measurement indicates power gain (S-21) of 10.55 similar to 12.6dB and noise figure (NF50) of 3.2 similar to 3.95 dB through the UWB (3 similar to 10.5GHz). This UWB LNA with small chip area (0.69mm(2)) provides a solution for low voltages, low power, and low cost.
Low Voltage and Low power UWB CMOS LNA using Current-Reused and Forward Body Biasing Techniques
(2017-01-01)
Guo, Jyh-Chyurn
;
Lin, Ching-Shiang
;
Liang, Yu-Tang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A ultra-wideband (UWB) low noise amplifier (LNA) was designed and fabricated in 0.18 mu m CMOS technology. The successful integration of current-reused and forward body biasing (FBB) techniques in a cascade amplifier can enable an aggressive scaling of the supply voltages, V-DD and V-G1 to 1.0V and 0.53V. The low voltage feature from FBB leads to more than 50% saving of power dissipation to 5.2mW. The measured power gain (S-21) can reach 10.55 similar to 12.6dB and noise figure (NF50) is 3.2 similar to 3.95 dB through the UWB (3 similar to 10.5GHz). This UWB LNA with small chip area (0.69mm(2)) provides a solution of low voltages, low power, and low cost.