Browsing by Author "Lin, HY"

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A compact DSP core with static floating-point arithmetic
(2006-02-01)
Lin, TJ
;
Lin, HY
;
Chao, CM
;
Liu, CW
;
Jen, CW
A multimedia system-on-a-chip (SoC) usually contains one or more programmable digital signal processors (DSP) to accelerate data-intensive computations. But most of these DSP cores are designed originally for standalone applications, and they must have some overlapped (and redundant) components with the host microprocessor. This paper presents a compact DSP for multi-core systems, which is fully programmable and has been optimized to execute a set of signal processing kernels very efficiently. The DSP core was designed concurrently with its automatic software generator based on high-level synthesis. Moreover, it performs lightweight arithmetic-the static floating-point (SFP), which approximates the quality of floating-point (FP) operations with the hardware similar to that of the integer arithmetic. In our simulations, the compact DSP and its auto-generated software can achieve 3X performance (estimated in cycles) of those DSP cores in the dual-core baseband processors with similar computing resources. Besides, the 16-bit SFP has above 40 dB signal to round-off noise ratio over the IEEE single-precision FP, and it even outperforms the hand-optimized programs based on the 32-bit integer arithmetic. The 24-bit SFP has above 64 dB quality, of which the maximum precision is identical to that of the single-precision FP. Finally, the DSP core has been implemented and fabricated in the UMC 0.18 mu m 1P6M CMOS technology. It can operate at 314.5 MHz while consuming 52mW average power. The core size is only 1.5 mmx1.5 mm including the 16 KB on-chip memory and the AMBA AHB interface.
A novel methodology for extracting effective density-of-states in poly-Si thin-film transistors
(2004)
Lin, HC
;
Yeh, KL
;
Lee, MH
;
Su, YC
;
Huang, TY
A novel methodology that greatly simplifies the procedure of extracting the effective density-of-states (DOS) in polycrystalline-Si thin-film transistors (poly-Si TFTs) is proposed and demonstrated. The characterization is performed on a Schottky barrier (SB) TFT with electrical source/drain extensions induced by a field-plate. Only one single device and two simple subthreshold I-V measurements at room temperature are needed for full band-gap DOS extraction. Impacts of different process treatments are clearly resolved using this methodology.
A novel structure for three-dimensional silicon magnetic transducers to improve the sensitivity symmetry
(1996-09-01)
Lin, HY
;
Lei, TF
;
Jeng, JJ
;
Pan, CL
;
Chang, CY
A three-dimensional silicon magnetic transducer with symmetric sensitivities in the x-, y- and z-directions and small cross sensitivity has been demonstrated. Devices are based on a design of a vertical Hall structure using the surrounding trench and symmetric design to suppress the cross sensitivity. The fabrication process is simple and can be used as a part of a standard integrated circuit process. The results show that almost equal sensitivities in all three components of magnetic field can be obtained by coating Ni/Co thin films on the backside of the substrates. The cross sensitivity is only 1.3% of the sensitivity.
A novel structure for three-dimensional silicon magnetic transducers to improve the sensitivity symmetry
(1996-09-01)
Lin, HY
;
Lei, TF
;
Jeng, JJ
;
Pan, CL
;
Chang, CY
A three-dimensional silicon magnetic transducer with symmetric sensitivities in the x-, y- and z-directions and small cross sensitivity has been demonstrated. Devices are based on a design of a vertical Hall structure using the surrounding trench and symmetric design to suppress the cross sensitivity. The fabrication process is simple and can be used as a part of a standard integrated circuit process. The results show that almost equal sensitivities in all three components of magnetic field can be obtained by coating Ni/Co thin films on the backside of the substrates. The cross sensitivity is only 1.3% of the sensitivity.
A vector-based spatial model for landfill siting
(1998-02-01)
Lin, HY
;
Kao, JJ
;
環境工程研究所
;
Institute of Environmental Engineering
An inappropriate landfill site may have negative environmental, economic or ecological impacts. Therefore, landfill siting should carefully consider various factors and regulations and evaluate a significant amount of spatial data. However, processing of spatial information for various siting factors is tedious. Digitized data is thus frequently used for improving data processing and analysis efficiency. Vector-based data are composed of points, lines and polygons, which express gee-referenced attributes of the real world. Compared to raster-based data, although describing real world spatial information more precisely, the lack of uniformity makes vector-based data difficult to use with a mathematical optimization model. In this study, a mixed-integer spatial optimization model is developed based on vector-based data to assist decision makers in finding a suitable site from a siting area. Major factors considered in the model include impacts on the environment, economic efficiency, and site compactness. A sample case is provided to demonstrate the effectiveness of the model. (C) 1998 Elsevier Science B.V.
An efficient solution to the millionaires' problem based on homomorphic encryption
(2005)
Lin, HY
;
Tzeng, WG
;
資訊工程學系
;
Department of Computer Science
We proposed a two-round protocol for solving the Millionaires' Problem in the setting of semi-honest parties. Our protocol uses either multiplicative or additive homomorphic encryptions. Previously proposed protocols used additive or XOR homomorphic encryption schemes only. The computation and communication costs of our protocol are in the same asymptotic order as those of the other efficient protocols. Nevertheless, since multiplicative homomorphic encryption scheme is more efficient than an additive one practically, our construction saves computation time and communication bandwidth in practicality.
Authentication of 3-D polygonal meshes
(2004)
Lin, HY
;
Liao, HYM
;
Lu, CS
;
Lin, JC
;
資訊工程學系
Designing a powerful fragile watermarking technique for authenticating 3-D polygonal meshes is a very difficult task. Yeo and Yeung [17] were first to propose a fragile watermarking method to perform authentication of 3-D polygonal meshes. Although their method can authenticate the integrity of 3-D polygonal meshes, it is unable to distinguish malicious attacks from incidental data processings. In this paper, we propose a new fragile watermarking method which not only is able to detect malicious attacks, but also is immune to incidental data processings. During the process of watermark embedding, mesh parameterization techniques are employed to perturb the coordinates of invalid vertices while cautiously maintaining the appearance of the original model. Since the proposed embedding method is independent of the order of vertices, the hidden watermark is immune to some attacks, such as vertex reordering. In addition, the proposed method can be used to perform region-based tampering detection. The experimental results have shown that the proposed fragile watermarking scheme is indeed powerful.
Comparison of N-2 and NH3 plasma passivation effects on polycrystalline silicon thin-film transistors
(1998-07-01)
Lee, YS
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Lin, HY
;
Lei, TF
;
Huang, TY
;
Chang, TC
The passivation effects of pure N-2 plasma on polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been studied and compared with those of NH3 plasma. We found that, similar to the recently-proposed NH3 plasma passivation, N-2 plasma passivation can also effectively improve device parameters such as field effect mobility, threshold voltage subthreshold swing, off current, and on/off current ratio. While the improvement of NH3-passivated devices can be attributed to both hydrogen and nitrogen passivation effects, nitrogen passivation alone is mainly responsible for the improvement of N-2-passivated devices. Zn addition, we round that N-2-passivated devices exhibit much better hot-carrier reliability than NH3-passivated devices. The better hot-carrier reliability of N-2-passivated devices can be explained by the formation of strong Si-N bonds which are difficult to break, while effectively eliminating the weaker N-H bonds, which are inevitable in NH3-passivated devices. The results of a Fourier. transform infrared (FTIR) spectrum analysis performed in this study are consistent with this proposition.
Distortion analysis of single V-groove butt welding on heat treatable aluminum alloys
(2005-09-01)
Cheng, CM
;
Chou, CP
;
Lee, IK
;
Lin, HY
;
機械工程學系
In this study we conducted single V-groove butt welding (GTAW) on three types of heat treatable aluminum alloys 2024-T351, 6061-T6 and 7075-T6 and compared the angular distortion levels of the three aluminum alloys at different Vee preparation angles with or without restraint. Experimental results demonstrated that when the Vee preparation angle was 0 degrees (l-shaped groove), the angular distortion level of the restrained weldment can exceed that of the unrestrained weldments. Moreover, when. the Vee preparation angle was 45 degrees, 60 degrees or 90 degrees, the restrained weldment had lower angular distortion than the unrestrained weldments. The single Vee preparation angle (amount of filler metal) in butt welding affected the angular distortion of the weldment. Without restraint, the angular distortion tended to increase with the single Vee preparation angle. Meanwhile, the angular distortion tended to decrease when the single Vee preparation angle was 60 degrees. Additionally, a restrained weldment had high angular distortion when the single Vee preparation angle was 0 degrees. Notably, the angular distortion tended to reduce with increasing single Vee preparation angle. The angular distortion of the weldment was minimized at an angle of 60 degrees. However, the angular distortion increased when the Vee preparation angle exceeded 60 degrees. The high-temperature yield strength of a material also affected its angular distortion. Angular distortion increased with high-temperature yield strength. Experimental results also showed that, from the strongest to the weakest, the high-temperature yield strength of the three types of aluminum alloys followed the order 6061-T6 and 2024-T351 > 7075-T6.
Effect of Ge incorporation on the performance of p-channel polycrystalline Si1-xGex thin-film transistors
(1996-05-01)
Lin, HC
;
Lin, HY
;
Chang, CY
;
電控工程研究所
;
奈米中心
In this study, p-channel polycrystalline silicon-germanium thin-film transistors (poly-Si1-xGex TFTs) with different Ge contents in the channel layer were fabricated and characterized. A novel device process was developed to fabricate the test samples. The device structure utilized the in situ boron-doped poly-Si0.79Ge0.21 with an extremely low resistivity (below 2 m Omega cm) as the source/drain and the undoped poly-Si (or Si1-xGex) as the channel layer. It is observed that the addition of Ge atoms in the channel would significantly increase the amount or trap density at grain boundaries thus degrading the device performance. Based on these results, we recommend the use of poly-Si1-xGex source/drain to reduce the contact resistance but do not recommend that it is appropriate to replace poly-Si as the channel material of TFTs.
Enhanced spatial model for landfill siting analysis
(1999-09-01)
Lin, HY
;
Kao, JJ
;
環境工程研究所
;
Institute of Environmental Engineering
A landfill siting analysis typically requires evaluating various rules, factors, constraints, and numerous spatial data. A modern geographical information system, although capable of rapidly processing a massive amount of spatial data, lacks the ability to locate an optimal site when compactness and other factors are simultaneously evaluated. A previously developed grid-based model could not be applied to resolve this inability for irregularly shaped spatial data. Therefore, an enhanced spatial siting model is proposed herein for general spatial data. A compactness index is applied to ensure the integrity of selected sites. Two case studies are presented to demonstrate the applicability of the proposed model. The proposed model and two models developed previously are compared in the first case study based on the single factor of land cost. A single factor model is perhaps quite unacceptable with respect to other factors. The second case study is thus presented to demonstrate the flexibility of the model for considering additional factors, land slope, and road network accessibility. Moreover, results obtained from various models and siting factors are compared and discussed.
Enhancement of the optical and electrical properties in InGaAlP/InGaP PIN heterostructures by rapid thermal annealing on misoriented substrate
(1996-07-01)
Chin, A
;
Lin, HY
;
Lin, BC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have studied the optical and electrical properties of InGaAlP/InGaP PIN heterostructures by the effects of post-growth annealing, substrate misorientation and growth temperature. For the as-grown p-type In-0.5(Ga0.5Al0.5)(0.5)P, the 15 degrees misoriented sample shows the largest hole concentration of 1 x 10(18) cm(-3) as compared to 20 and 10 degrees misoriented samples. After annealing at 900 degrees C for 30 s, the hole concentration increases about three times to 2.6 x 10(18) cm(-3). The increased hole concentration is related to the four times enhanced photoluminescence (PL) intensity. In the In0.6Ga0.4P/In-0.5(Ga0.6Al0.4)(0.5)P stained multiple quantum wells, the post-growth annealing also improves the PL integrated intensity. The PL intensity on an as-grown sample decreases with the increased degree of misorientation, while the PL peak energy increases with the increased degree of misorientation, from 0 degrees, 2 degrees, 10 degrees toward 15 degrees. The PL intensities are larger for samples grown at 760 degrees C than those grown at 700 degrees C. Copyright (C) 1996 Elsevier Science Ltd.
Enhancement of the optical and electrical properties in InGaAlP/InGaP PIN heterostructures by rapid thermal annealing on misoriented substrate
(1996-07-01)
Chin, A
;
Lin, HY
;
Lin, BC
;
交大名義發表
;
電子工程學系及電子研究所
We have studied the optical and electrical properties of InGaAlP/InGaP PIN heterostructures by the effects of post-growth annealing, substrate misorientation and growth temperature. For the as-grown p-type In-0.5(Ga0.5Al0.5)(0.5)P, the 15 degrees misoriented sample shows the largest hole concentration of 1 x 10(18) cm(-3) as compared to 20 and 10 degrees misoriented samples. After annealing at 900 degrees C for 30 s, the hole concentration increases about three times to 2.6 x 10(18) cm(-3). The increased hole concentration is related to the four times enhanced photoluminescence (PL) intensity. In the In0.6Ga0.4P/In-0.5(Ga0.6Al0.4)(0.5)P stained multiple quantum wells, the post-growth annealing also improves the PL integrated intensity. The PL intensity on an as-grown sample decreases with the increased degree of misorientation, while the PL peak energy increases with the increased degree of misorientation, from 0 degrees, 2 degrees, 10 degrees toward 15 degrees. The PL intensities are larger for samples grown at 760 degrees C than those grown at 700 degrees C. Copyright (C) 1996 Elsevier Science Ltd.
Fabrication of thin film transistors by chemical mechanical polished polycrystalline silicon films
(1996-03-01)
Chang, CY
;
Lin, HY
;
Lei, TF
;
Cheng, JY
;
Chen, LP
A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP), In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm(2)/V-s, ON/OFF current ratio of 1.110(7), and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's.
Fuzzy GIS assisted landfill siting analysis
(1996)
Lin, HY
;
Kao, JJ
;
Li, KC
;
Hwang, HY
;
交大名義發表
This paper presents a prototypical fuzzy geographical information system (GIS) developed to facilitate landfill siting analysis. Landfill siting requires extensive effort to process massive spatial information, to evaluate various factors, and to review numerous criteria and regulations. A computerized GIS, although capable of effectively manipulating spatial information, generally lacks the ability to evaluate the suitability levers of candidate sites based on factors/criteria with some degree of imprecision and/or uncertainty. Because of their imprecision/uncertainty, many siting factors/criteria are not appropriate to be evaluated with a binary assessment, e.g., yes/no. Fuzzy set algorithms are therefore applied to overcome this difficulty. With proper membership functions assigned to imprecise/uncertain factors/criteria, the suitability score of a candidate site can be determined by a series of fuzzy calculations. The algorithms are incorporated into a previously developed landfill siting GIS to assist an engineer in improving siting decisions. This article, in addition to the description of the prototype, presents a case study to demonstrate the effectiveness of the developed Fuzzy GIS.
Grid-based heuristic method for multifactor landfill siting
(2005-10-01)
Lin, HY
;
Kao, JJ
;
環境工程研究所
;
Institute of Environmental Engineering
Siting a landfill requires the processing of a large amount of spatial data. However, the manual processing of spatial data is tedious. A geographical information system (GIS), although capable of handling spatial data in siting analyses, generally lacks an optimization function. Optimization models are available for use with a GIS, but they usually have difficulties finding the optimal site from a large area within an acceptable computational time, and not easily directly available with a raster-based GIS. To overcome this difficulty, this study developed a two stage heuristic method. Multiple factors for landfill siting are considered and a weighted sum is computed for evaluating the suitability of a candidate site. The method first finds areas with significantly high potentialities and then applies a previously developed mixed-integer programming model to locate the optimal site within the potential areas, and can significantly reduce the computational time required for resolving a large siting problem. A case study was implemented to demonstrate the effectiveness of the proposed method, and a comparison with the previously developed model was provided and discussed.
Hot cracking of welds on heat treatable aluminium alloys
(2005-06-01)
Cheng, CM
;
Chou, CP
;
Lee, IK
;
Lin, HY
;
機械工程學系
The Spot Varestraint test was used to evaluate the hot cracking susceptibility of several aluminium alloys namely 6061-T6, 6061-T6 ( H), 7075-T6, 7075-T6 ( H). The effects of augment strain, the number of thermal cycles and cold working ( rolling) on the cracking susceptibility were investigated, and the total crack length was used to evaluate the hot cracking susceptibility. The results indicate that the number of thermal cycles is irrelevant to the hot cracking susceptibility in the weld fusion zone, but does affect this susceptibility in the heat affected zone (HAZ). More thermal cycles correspond to larger hot cracks in the HAZ, especially in the weld metal HAZ. The hot cracking susceptibility of materials increased with augment strain in both the fusion zone and the HAZ. Cold working of the materials can reduce their hot cracking susceptibility. The hot cracking susceptibility of 7075-T6 aluminium alloys is higher than that of 6061-T6. There was significant Cu segregation in the HAZ of 7075-T6 aluminium alloy, resulting in a higher susceptibility to hot cracking in this zone.
Lightweight arithmetic units for VLSI digital signal processors
(2005)
Ou, SH
;
Lin, TJ
;
Lin, HY
;
Chao, CM
;
Liu, CW
This paper presents a lightweight arithmetic for embedded signal processing, whose hardware complexity is similar to that of the integer one. In our simulations, its 16-bit version has 40.18dB signal to round-off error ratio over the IEEE single-precision floating-point arithmetic, which even out-performs the hand-optimized 32-bit code with integer arithmetic.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.