Browsing by Author "Lin, Horng-Chih"

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100-nm IGZO Thin-Film Transistors With Film Profile Engineering
(2014-06-01)
Lin, Horng-Chih
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Shie, Bo-Shiuan
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
100-nm indium-gallium-zinc-oxide (IGZO) thin-film transistors were fabricated with a one-mask process, which takes the advantage of photoresist trimming technique and the concept of film profile engineering (FPE). With I-line-based photolithography, a device with channel length of 97 nm has been successfully fabricated. The FPE device contains a conformal Al2O3 gate oxide, concave IGZO channel, and discrete source/drain (S/D) Al contacts. Good device characteristics including a high-ON/OFF current ratio (>10(7)) and good subthreshold swing (140 mV/decade) are obtained. Nonetheless, high-S/D series resistance presents a key issue that needs to be addressed for further device performance improvement.
A carbon nanotube field effect transistor with tunable conduction-type by electrostatic effects
(2006-07-01)
Chen, Bae-Horng
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Wei, Jeng-Hua
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Lo, Po-Yuan
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Wang, Hung-Hsiang
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Lai, Ming-Jinn
In this paper, we report a conduction-type-tunable carbon nanotube field effect transistor (CNT-FET) with double-gate structure (DG CNT-FET). In this study, a specially designed narrow top-gate is created to modulate the energy band in the middle region of a single CNT. In the proposed DG device structure, the top-gate and bottom-gate biases exhibit independent modulation behaviors. Depending on whether a positive or negative bias is applied to the top-gate, the CNT-FET can be operated in either n- or p-type conduction. Energy band diagram conducive to the physical mechanisms of the proposed DG CNT-FET device structure is proposed. Based on the proposed hypothesis, ambipolar CNT-FETs can indeed be converted to n- or p-type-like behaviors. (c) 2006 Elsevier Ltd. All rights reserved.
A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO(2)/poly-gate complementary metal oxide semiconductor technology
(2010-04-01)
Weng, Wu-Te
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Lee, Yao-Jen
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Lin, Horng-Chih
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
This study examines the effects of plasma-induced damage (PID) both on advanced SiO(2)/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO(2)/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. (C) 2010 Elsevier Ltd. All rights reserved.
A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO2/poly-gate complementary metal oxide semiconductor technology
(2010-04-01)
Weng, Wu-Te
;
Lee, Yao-Jen
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
This study examines the effects of plasma-induced damage (PID) both on advanced SiO2/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. (C) 2010 Elsevier Ltd. All rights reserved.
A Film-Profile-Engineered 3-D InGaZnO Inverter Technology With Systematically Tunable Threshold Voltage
(2016-09)
Lyu, Rong-Jhe
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Lin, Horng-Chih
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Li, Pei-Wen
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
In this paper, a new depletion-load metal oxide-based inverter with 3-D structure is realized with film-profile-engineered InGaZnO (IGZO) thin-film transistors (TFTs). The proposed inverter possesses vertically stacked load and drive TFTs whose threshold voltage can be flexibly adjusted into a wide range of -2.3-1 V through merely adjusting the geometric parameters without the necessity of additional processes or masks. The 3-D IGZO inverters constructed through the proposed technology demonstrate full-swing switching with voltage gains up to 19 V/V under an operation voltage of 9 V. The 3-D inverters can not only reduce the footprint but also promote the resistance toward light-induced instability.
A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires
(2012-02-29)
Su, Chun-Jung
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Su, Tuan-Kai
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Tsai, Tzu-I
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Lin, Horng-Chih
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Huang, Tiao-Yuan
In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n(+)-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.
A New High Voltage IC with Robust Isolation Design
(2018-01-01)
Ningaraju, Vivek
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Lin, Horng-Chih
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Chen, Po-An
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Wen, Jiin-Shiarng
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交大名義發表
A new and robust isolation design for control devices integrated in the high side island region of 250V high-voltage integrated circuits (HVIC) is proposed and verified by numerical calculations, simulations and experiments. The new isolation structure can be realized using micro N-well in the P-type isolation region to achieve a higher breakdown voltage (BV). The measurement and TCAD simulation results prove this new isolation structure's BV is over 350V with negligible leakage current. In the proposed scheme BV is improved by 15% more than the conventional structure without adding additional process steps and photo layers.
A New Methodology for Probing the Electrical Properties of Heavily Phosphorous-Doped Polycrystalline Silicon Nanowires
(2013-04-01)
Lin, Horng-Chih
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Lin, Zer-Ming
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this study, we proposed a new methodology for probing the electrical properties of heavily doped polycrystalline silicon (poly-Si) nanowires (NWs), including active doping concentration, mobility, and interface fixed charge density. Implementation of this procedure is based on the modulation of the device operation of a gate-all-around (GAA) junctionless (J-less) transistor from the gated resistor mode to the ungated one. The extracted carrier concentration in the NW is found to be much lower than that of Hall measurements, while a negative fixed charge density is identified with the procedure. Dopant segregation at the oxide interface is postulated to be closely related to these observations. (C) 2013 The Japan Society of Applied Physics
A Novel Charge-Trapping-Type Memory With Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer
(2013-03-01)
Lee, Ko-Hui
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Lin, Horng-Chih
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Hf-based charge-trapping (CT) layers, including HfO2 and HfAlO, were employed in the fabrication of a CT-type memory with gate-all-around (GAA) poly-Si nanowire channels. It is shown that the GAA configuration can greatly enhance the programming/erasing efficiency as compared with the conventional planar scheme. It is also shown that the incorporation of Al into the dielectric can further improve the retention and endurance characteristics over the counterparts with a HfO2 trapping layer. Retardation of the recrystallization of the dielectric film with Al incorporation is postulated to be responsible for these observations.
A Novel Double-gated Nanowire TFT and Investigation of Its Size Dependency
(2009)
Chen, Wei-Chen
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Lin, Chuan-Ding
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Lin, Horng-Chih
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
A simple method for fabricating poly-Si nanowire (NW) TFT with multiple gates is proposed and characterized. In this structure, NW is formed mainly using both anisotropic and highly selective isotropic plasma etching. It is found that when the size of NW is scaled down, double-gated operation provides more improvement. Furthermore, by utilizing this unique independent double-gated Configuration, the function of threshold voltage modulation is investigated.
A novel multiple-gate polycrystalline silicon nanowire transistor featuring an inverse-T gate
(2008-07-01)
Lin, Horng-Chih
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Hsu, Hsing-Hui
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Su, Chun-Jung
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T-gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of single-gate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at Vd = 2 V is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.
A novel photoresist-based film-profile engineering scheme for fabricating double-gated, recess-channel IGZO thin-film transistors
(2020-04-01)
Huang, Yu-An
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Peng, Kang-Pin
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Meng, Yu-Chiao
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Su, Chun-Jung
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Li, Pei-Wen
We reported an experimental fabrication of double-gated (DG) thin-film transistor (TFT) with IGZO recess-channel using a designer photoresist-based thin-film profile engineering approach. In this approach, an organic shadow mask of photoresist (PR) was formed over a p(+)-Si wafer that was encapsulated by an oxide layer, The lithographically-patterned PR layer is an effective mask for shadowing reactive species during the subsequent deposition steps of IGZO and Aluminum, enabling the formation of IGZO recess-channel and discrete Al source/drain pads at room temperature. The top-gate or DG configurations with the Si substrate serving as the bottom-gate were investigated. The fabricated DG TFTs show significant; improvements in both I-ON and I-OFF as compared with single-gated TFTs. The proposed process scheme is readily applicable to the back-end-of-line of a chip. This work demonstrates the feasibility of IGZO recess-channel TFTs in various gated configurations, enabling a building block for emerging functional devices for More-than-Moore applications. (C) 2020 The Japan Society of Applied Physics
A novel poly-Si nanowire TFT for nonvolatile memory applications
(2008)
Hsu, Hsin-Hwei
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Lin, Horng-Chih
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Huang, Jian-Fu
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Huang, Tiao-Yuan
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電子工程學系及電子研究所
A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.
A Novel Scheme for Fabricating CMOS Inverters With Poly-Si Nanowire Channels
(2012-06-01)
Kuo, Chia-Hao
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Lin, Horng-Chih
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Lee, I-Che
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Cheng, Huang-Chung
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Huang, Tiao-Yuan
A novel complementary metal-oxide-semiconductor inverter with poly-Si nanowire channels is proposed and demonstrated in this letter. The scheme employs a clever tilted-angle implant process in the fabrication; therefore, the formation of the source and drain of both p-channel and n-channel devices requires only one lithographic step. The fabricated n-channel and p-channel field-effect transistors in the inverters show a high ON/OFF current ratio, an acceptable subthreshold swing, and a symmetric driving current, thus enabling the realization of excellent characteristics of the inverters.
A Novel Three-Dimensional Submicron ZnO Inverter Technology with Refined Contact Design
(2019-01-01)
Lin, Horng-Chih
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Kuan, Chin-I
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Impact of source/drain contacts on the operation performance of three-dimensional (3-D) zinc-oxide (ZnO) logic inverters is explored in this work. The 3-D inverters consisting of a load vertically stacking on a driver were constructed with the film-profile-engineered (FPE) approach. Use of an ultrathin ZnON contact layer is proposed and demonstrated to be effective in reducing the source/drain (S/D) series resistances (RSD) of the devices. From the material characterization, the improvement in the electrical characteristics is attributed to the suppression of an insulating interfacial oxide layer present at the contact interface which may impede the carrier transport. Measurement results of inverters indicate that the voltage gain can be improved from 9.7 V/V to 13.2 V/V as the scheme is implemented.
A Platform with Exquisite Film Profile Engineering in Oxide-Based Thin-Film Transistors for More-than-Moore Applications
(2019-01-01)
Lin, Horng-Chih
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Huang, Yu-An
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Recently we proposed and developed a unique film profile engineering (FPE) scheme for the fabrication of high-performance sub-micron oxide-semiconductor TFTs. In this scheme, profiles of the three pivotal thin films contained in a device, including gate oxide, oxide-semiconductor channel, and source/drain metal films, can be effectively tailored by selecting proper deposition tools with tunable process conditions. The fabricated IGZO, ZnO, and ZnON devices show decent performance in terms of high on/off current ratio (>10(8)) and steep subthreshold swing (<100 mV/dec). Since the low-temperature and the mature processes involved are highly compatible to the modern IC manufacturing, the fabricated devices can be readily integrated into the back-end-of-line (BEOL) of an advanced chip, making the FPE scheme useful and potential for a number of emerging applications in the more-than-Moore era.
A simple method for sub-100 nm pattern generation with I-line double-patterning technique
(2010-05-01)
Tsai, Tzu-I
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Lin, Horng-Chih
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Jian, Min-Feng
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Huang, Tiao-Yuan
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Chao, Tien-Sheng
We have developed a simple method adopting double-patterning technique to extend the I-line stepper limit for the sub-100 nm poly-Si pattern generation in this work. Through in-line and cross-sectional scanned electron microscopic analyses of the generated patterns, we confirmed the feasibility of the double-patterning technique for the fabrication of nano-scale devices. Resolution capability of this technique has been confirmed to be at least 100 nm, which is much superior to the resolution limit of conventional I-line lithography. This approach has also been applied for fabricating p-channel metal-oxide-semiconductor field-effect transistors. Excellent device characteristics were verified. (C) 2010 Elsevier Ltd. All rights reserved.
A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors
(2010-10-29)
Chen, Wei-Chen
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Lin, Horng-Chih
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Lin, Zer-Ming
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Hsu, Chin-Tsai
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Huang, Tiao-Yuan
Employing mix-and-match lithography of I-line stepper and e-beam direct writing, independent double-gated poly-Si nanowire thin film transistors with channel lengths ranging from 70 nm to 5 mu m were fabricated and characterized. Electrical measurements performed under cryogenic ambient displayed intriguing characteristics in terms of length dependent abrupt switching behavior for one of the single-gated modes. Through simulation and experimental verification, the root cause for this phenomenon was identified to be the non-uniformly distributed dopants introduced by ion implantation.
A study on low temperature transport properties of independent double-gated poly-Si nanowire transistors
(2010-10-29)
Chen, Wei-Chen
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Lin, Horng-Chih
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Lin, Zer-Ming
;
Hsu, Chin-Tsai
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Huang, Tiao-Yuan
Employing mix-and-match lithography of I-line stepper and e-beam direct writing, independent double-gated poly-Si nanowire thin film transistors with channel lengths ranging from 70 nm to 5 mu m were fabricated and characterized. Electrical measurements performed under cryogenic ambient displayed intriguing characteristics in terms of length dependent abrupt switching behavior for one of the single-gated modes. Through simulation and experimental verification, the root cause for this phenomenon was identified to be the non-uniformly distributed dopants introduced by ion implantation.
An innovative understanding of metal-insulator-metal (MIM)-capacitor degradation under constant-current stress
(2007-09-01)
Hung, Chi-Chao
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Oates, Anthony S.
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Lin, Horng-Chih
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Chang, Yu-En Percy
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Wang, Jia-Lian
This paper provides a new understanding of metal-insulator-metal-capacitor-degradation behavior under a wide range of constant-current-stress conditions. It was found that capacitance degrades with stress, but the behavior of the degradation strongly depends on the stress-current density. At high stress levels, the capacitance increases logarithmically as the injection charge increases until dielectric breakdown occurs. At lower stress conditions, the degradation rate is proportional to the stress current and reverses after a certain period of time. A metal-insulator interlayer is observed using cross-sectional transmission-electron-microscopy micrographs, which possibly explains this reversal phenomenon.