Browsing by Author "Lin, Jian-Hong"

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Characterization of the low temperature activated N(+)/P junction formed by implant into silicide method
(2008-07-30)
Chang, Kow-Ming
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Lin, Jian-Hong
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Yang, Chih-Hsiang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Shallow junction formation and low thermal budget control are important for advanced device manufacturing. Implant into silicide (IIS) method is a candidate to achieve both requirements. In this work we show that the high activation ability of the implant into nickel silicide method at low activated temperature is strongly related to the solid phase epitaxial regrowth (SPER) process. The SIMS, capacitance-voltage (C-V), four points probe (FPP), and current-voltage (I-V) measurements are combined to demonstrate that the SPER process of the IIS method is starting from the silicide/silicon (M/S) interface. The best N(+)/P interface is formed when SPER is complete. After SPER process finished, additional thermal budget may cause junction performance degradation at the temperature higher than 550 degrees C. (C) 2008 Elsevier B. V. All rights reserved.
Characterization of the low temperature activated P+/N junction formed by implant into silicide method
(2007)
Chang, Kow-Ming
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Lin, Jian-Hong
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Yang, Chih-Hsiang
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Characterization of the low temperature dopant activation behavior at NiSi/silicon interface formed by implant into silicide method
(2008-07-30)
Chang, Kow-Ming
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Lin, Jian-Hong
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Sun, Cheng-Yen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Process temperature and thermal budget control are very important for high-k dielectric device manufacturing. This work focuses on the characteristics of low temperature activated nickel silicide/silicon (M/S) interface formed by implant into silicide (IIS) method. By combining SIMS, C-V, I-V, and AFM measurements in this work, it provides a clear picture that the high dopant activation ratio can be achieved at low temperature (below 600 degrees C) by IIS method. From SIMS and C-V measurements, high dopant activation behavior is exhibited, and from I-V measurement, the ohmic contact behavior at the M/ S junction is showed. AFM inspection displays that under 2nd RTA 700 degrees C 30 s no agglomeration occurs. These results suggest that IIS method has the potential to integrate with high-k dielectric due to its low process temperature. It gives an alternate for future device integration. (C) 2008 Elsevier B. V. All rights reserved.
Investigation of Microwave Assisted Annealing on AP-PECVD Fabricated In-Ga-Zn-O Thin Film Transistors under Positive Bias Temperature Stress
(2016)
Wu, Chien-Hung
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Huang, Bo-Wen
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Chang, Kow-Ming
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Cheng, Chia-Yao
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Chen, Hsin-Ying
In this paper, microwave assisted annealing (MWAA) technique on atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) fabricated indium-gallium-zinc-oxide thin-film transistors (IGZO TFTs) is investigated for the first time. MWAA with 300W for 100sec treatment on AP-IGZO TFTs have been fabricated successfully and show excellent electrical characteristics including a VTH of -1.23 V, SS of 0.18 V/dec, mu FE of 17.4 cm2/V-s, and Ion/Ioff ratio of 8.14 106. Stretched exponential time dependence model is used to analyze the mechanism of AP-IGZO TFTs under PBTI stress. Accordingly, chemisorption model for oxygen adsorption at AP-IGZO backchannel with and without MWAA is proposed to explain the mechanism under PBTI stress.
Oxygen-Dependent Instability and Annealing/Passivation Effects in Amorphous In-Ga-ZnO Thin-Film Transistors
(2011-11-01)
Chen, Wei-Tsung
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Lo, Shih-Yi
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Kao, Shih-Chin
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Zan, Hsiao-Wen
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Tsai, Chuang-Chuang
This letter discusses the reason for the instability of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) under both positive and negative bias stresses. This instability is significantly influenced by the oxygen content in the bulk IGZO and the surrounding environment. The as-fabricated low-temperature devices can only endure a single polarized bias stress. An a-IGZO TFT that is stable toward both positive and negative bias stresses with large relaxation times of 95 x 10(4) and 371 x 10(4) s, respectively, is achieved by annealing and passivation.
Study on Oxygen-dependent Instability of Amorphous In-Ga-Zn-O TFT and Completely Stable Device under Both Positive and Negative Bias Stresses
(2010)
Chen, Wei-Tsung
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Zan, Hsiao-Wen
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Lo, Shih-Yi
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Kao, Shih-Chin
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Tsai, Chuang-Chuang
A complete experiment is conducted to verify the origin of stress-induced instability in an amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT). It is found that the oxygen ratio in an IGZO layer strongly influences the device stability under bias stress. For realizing an adequately stable device, post-annealing and passivation are performed in order.
The Performance Improvement of N-2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel
(2016-06)
Wu, Chien-Hung
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Huang, Bo-Wen
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Chang, Kow-Ming
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Wang, Shui-Jinn
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Lin, Jian-Hong
The aim of this paper is to illustrate the N-2 plasma treatment for high-kappa ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N-2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N-2 plasma treatment with field-effect mobility (mu(FET)) of 22.5 cm(2)/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I-on/I-off) of 1.49x10(7).