Browsing by Author "Lin, Yen-Chuan"

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3D Synaptic Architecture with Ultralow sub-10 fJ Energy per Spike for Neuromorphic Computation
(2014)
Wang, I-Ting
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Lin, Yen-Chuan
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Wang, Yu -Fen
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Hsu, Chung-Wei
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Hou, Tuo-Hung
A high-density 3D synaptic architecture based on self-rectifying Ta/TaOx/TiO2/Ti RRAM is proposed as an energy- and cost-efficient neuromorphic computation hardware. The device shows excellent analog synaptic features that can be accurately described by the physical and compact models. Ultra-low energy consumption comparable to that of a biological synapse (<10 fJ/spike) has been demonstrated for the first time.
Characterization and Modeling of Nonfilamentary Ta/TaOx/TiO2/Ti Analog Synaptic Device
(2015-05-08)
Wang, Yu-Fen
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Lin, Yen-Chuan
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Wang, I-Ting
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Lin, Tzu-Ping
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Hou, Tuo-Hung
A two-terminal analog synaptic device that precisely emulates biological synaptic features is expected to be a critical component for future hardware-based neuromorphic computing. Typical synaptic devices based on filamentary resistive switching face severe limitations on the implementation of concurrent inhibitory and excitatory synapses with low conductance and state fluctuation. For overcoming these limitations, we propose a Ta/TaOx/TiO2/Ti device with superior analog synaptic features. A physical simulation based on the homogeneous (nonfilamentary) barrier modulation induced by oxygen ion migration accurately reproduces various DC and AC evolutions of synaptic states, including the spike-timing-dependent plasticity and paired-pulse facilitation. Furthermore, a physics-based compact model for facilitating circuit-level design is proposed on the basis of the general definition of memristor devices. This comprehensive experimental and theoretical study of the promising electronic synapse can facilitate realizing large-scale neuromorphic systems.
RRAM SET Speed-Disturb Dilemma and Rapid Statistical Prediction Methodology
(2012)
Luo, Wun-Cheng
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Liu, Jen-Chieh
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Feng, Hsien-Tsung
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Lin, Yen-Chuan
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Huang, Jiun-Jia
This paper presents a first comprehensive study of SET speed-disturb dilemma in RRAM using statistically-based prediction methodologies. A rapid ramped-voltage stress based on percolation model and power-law V-t dependence showed excellent agreement with the time-consuming constant-voltage stress, and was applied to evaluate current status of RRAM devices in the literature.
Statistical Model and Rapid Prediction of RRAM SET Speed-Disturb Dilemma
(2013-11-01)
Luo, Wun-Cheng
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Liu, Jen-Chieh
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Lin, Yen-Chuan
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Lo, Chun-Li
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Huang, Jiun-Jia
A comprehensive study of SET speed-disturb dilemma in resistive-switching random access memory (RRAM) is presented using statistically based prediction methodologies, accounting for the stochastic nature of SET. An analytical percolation model has been successful in explaining the statistical Weibull distribution of SET time and SET voltage in addition to the power-law voltage-time dependence. Two prediction methodologies using constant voltage stress (CVS) and ramp voltage stress (RVS) are proposed to evaluate the SET speed-disturb properties. The RVS method reduces analysis time and cost and yields equivalent results as the CVS method. Furthermore, the RVS method is used to evaluate the device design space and the current status of RRAM technology to meet the strict requirement of the SET speed-disturb dilemma.