Browsing by Author "Lin, Yu-Hsien"

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Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application
(2014-10-28)
Chin, Fun-Tat
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Lin, Yu-Hsien
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You, Hsin-Chiang
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Yang, Wen-Luh
;
Lin, Li-Min
This study investigates an advanced copper (Cu) chemical displacement technique (CDT) with varying the chemical displacement time for fabricating Cu/SiO2-stacked resistive random-access memory (ReRAM). Compared with other Cu deposition methods, this CDT easily controls the interface of the Cu-insulator, the switching layer thickness, and the immunity of the Cu etching process, assisting the 1-transistor-1-ReRAM (1T-1R) structure and system-on-chip integration. The modulated shape of the Cu-SiO2 interface and the thickness of the SiO2 layer obtained by CDT-based Cu deposition on SiO2 were confirmed by scanning electron microscopy and atomic force microscopy. The CDT-fabricated Cu/SiO2-stacked ReRAM exhibited lower operation voltages and more stable data retention characteristics than the control Cu/SiO2-stacked sample. As the Cu CDT processing time increased, the forming and set voltages of the CDT-fabricated Cu/SiO2-stacked ReRAM decreased. Conversely, decreasing the processing time reduced the on-state current and reset voltage while increasing the endurance switching cycle time. Therefore, the switching characteristics were easily modulated by Cu CDT, yielding a high performance electrochemical metallization (ECM)-type ReRAM.
Automated Segmentation of Dental Calculus in Optical Coherence Tomography Images
(2018-01-01)
Lee, Chia-Yen
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Chuang, Ching-Cheng
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Chen, Guan-Jie
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Huang, Chih-Chia
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Lee, Shyh-Yuan
The presence of dental calculus is highly correlated with the formation and advancement of periodontal disease. The occurrence and relapse of periodontal disease can be prevented only if dental calculus is completely removed. In this study, optical coherence tomography (OCT) is used to obtain two-dimensional cross-sectional images of tooth samples, in conjunction with a segmentation technique that enables automatic identification of dental calculus. We propose the vertical intensity transform function to correct the nonuniform instrument signal intensity caused by OCT. Afterwards, the detection ranges are defined by K-means or the Markov random field (MRF), and the candidate range is selected on the basis of mathematical morphology (MM). Finally, the features (thickness gradient, texture, and tooth surface slope) are quantified, and dental calculus is recognized and segmented. In the preliminary result, the sensitivity is 87.5%. The mean distance between the boundaries generated by the proposed algorithm and the corresponding manually delineated boundaries is 2.52 +/- 3.54 pixels. Our proposed algorithm assists physicians to determine dental calculus more easily. Doctors no longer need to rely solely on their experiences to recognize dental calculus, but can refer to specific data to assist in diagnosis.
Demonstration of HfO2-Based Gate Dielectric With Low Interface State Density and Sub-nm EOT on Ge by Incorporating Ti Into Interfacial Layer
(2019-02-01)
Tsai, Yi-He
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Chou, Chen-Han
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Chung, Yun-Yan
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Yeh, Wen-Kuan
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Lin, Yu-Hsien
HfO2-based gate stacks with titanium (Ti) incorporated into a GeOx interfacial layer (IL) were fabricated on p-Ge substrates. X-ray photoelectron spectroscopy results, incorporating Ti, can efficiently suppress the GeO volatilization. This contributed to achievement of an equivalent oxide thickness of approximately 0.8 nm, a low interface states density D-it of approximately 2.5 x 10(11) eV(-1)cm(-2), and a smaller D-it increment of approximately 1 x 10(11) eV(-1)cm(-2) after constant negative voltage stress at a field of 8 MV/cm. Therefore, Ti is appropriate for improving the quality of GeOx through high temperature annealing.
Estimating the Detection Stability of a Si Nanowire Sensor Using an Additional Charging Electrode
(2013)
Chen, Min-Cheng
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Chen, Hsiao-Chien
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Lee, Ta-Hsien
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Lin, Yu-Hsien
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Shih, Jyun-Hung
This paper proposes a sensing stability estimation method that involves using an additional forcing electrode to simulate the surface charge coupling effect for bottom gate nanowire sensors. The alteration of the Si nanowire can be observed by using the charging electrode without any complex surface treatment and micro-channel setup. The nanowire sensor has a distinct charge-sensitive slope (V-th shift > 60 mV/10(-16)C) with a wire-width scaling of 35 nm. The proposed estimation technique simplifies the charge sensing operation.
Experimental Realization of Thermal Stability Enhancement of Nickel Germanide Alloy by Using TiN Metal Capping
(2017-05-01)
Chou, Chen-Han
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Tsai, Yi-He
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Hsu, Chung-Chun
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Jau, Yu-Hau
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Lin, Yu-Hsien
In this paper, we demonstrated the enhancement of thermal stability of nickel germanide (NiGe) alloy up to 600 degrees C by using titanium nitride (TiN) metal capping. A high ION/IOFF ratio of 2.9 x 105 was achieved by capping TiN metal on Ni for NiGe alloy formation at 600 degrees C. Detailed analyses were performed for realizing the mechanism for TiN capping on NiGe/Ge, including vertical element diffusion profile observation through depth-profiling X-ray photoelectron spectroscopy (XPS), element diffusion distribution by energy-dispersive X-ray spectroscopy mapping, and direct junction leakage current path detection by conductive atomic force microscopy. The experimental results indicated that TiN capping can reduce the risk of agglomeration and form a graded NiGe/Ge Schottky junction that is beneficial for suppressing the degradation of junction leakage. Subsequently, we compared the electrical performance of TiN/NiGe/n-Ge at various N/Ti ratios of TiNs. Based on the depth-profiling XPS results and electrical performance, TiN with an N/Ti ratio of approximately 1: 1 can resist the Ni and Ge diffusion, which facilitates the suppression of the agglomeration process. However, the TiN capping layers with an N/Ti ratio of less than approximately 1:1 (Ti-rich) were not favorable for resisting Ni and Ge diffusion.
HfO2 nanocrystal memory on SiGe channel
(2013-02-01)
Lin, Yu-Hsien
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Chien, Chao-Hsin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This study proposes a novel HfO2 nanocrystal memory on epi-SiGe (Ge: 15%) channel. Because SiGe has a smaller bandgap than that of silicon, it increases electron/hole injection and the enhances program/erase speeds. This study compares the characteristics of HfO2 nanocrystal memories with different oxynitride tunnel oxide thicknesses on Si and epi-SiGe substrate. Results show that the proposed nonvolatile memory possesses superior characteristics in terms of considerably large memory window for two-bits operation, high speed program/erase for low power applications, long retention time, excellent endurance, and strong immunity to disturbance. (C) 2012 Elsevier Ltd. All rights reserved.
High-Performance Double-Layer Nickel Nanocrystal Memory by Ion Bombardment Technique
(2013-10-01)
Liu, Sheng-Hsien
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Yang, Wen-Luh
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Lin, Yu-Hsien
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Wu, Chi-Chang
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Chao, Tien-Sheng
A novel ion bombardment (IB) technique is presented to fabricate and embed double-layer (DL) Ni nanocrystal (NC) in silicon nitride for TaN/Al2O3/Si3N4/SiO2/Si nonvolatile memory applications. In contrast to other methods of forming DL metal NC, the IB technique is a relatively simple fabrication method and completely compatible with the current IC manufacturing technologies. Using the IB technique, a high-quality ultrathin interlayer between top and bottom layered NCs can be easily formed and controlled. Compared with the control sample, the IB-induced DL Ni NC memory exhibits superior performance in terms of faster program and erase (P/E) speeds, longer data retention, better endurance, negligible program disturbance, and great potential for a multilevel operation. In addition, the IB-induced DL Ni NC device also shows higher P/E efficiency as well as similar excellent reliability by comparison with other conventional DL metal NC memories due to the high-quality ultrathin interlayer.
High-Performance Schottky Contact Quantum-Well Germanium Channel pMOSFET With Low Thermal Budget Process
(2016-01-01)
Hsu, Chung-Chun
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Tsai, Yi-He
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Chen, Che-Wei
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Li, Jyun-Han
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Lin, Yu-Hsien
We present a high-performance Si/Ge/Si p-channel metal-oxide-semiconductor field-effect transistor (pMOSFET) with a NiSiGe Schottky junction source/drain (S/D) formed through microwave-activated annealing. A Schottky contact S/D is preferable, because the lower process temperature is beneficial for eliminating Ge diffusion. The fabricated NiSiGe Schottky junction exhibited a high effective barrier height (Phi(Bn)) of 0.69 eV for electrons, resulting in a high junction current ratio of more than 10(5) at the applied voltage of vertical bar V-a vertical bar = 1 V. Our quantum-well pMOSFET exhibited a high I-ON/I-OFF ratio of similar to 10(7) (I-S) and a moderate subthreshold swing of 166 mV/decade.
Impact of channel dangling bonds on reliability characteristics of flash memory on poly-Si thin films
(2007-04-01)
Lin, Yu-Hsien
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Chien, Chao-Hsin
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Chou, Tung-Huan
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Chao, Tien-Sheng
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Lei, Tan-Fu
In this letter, we fabricated the poly-Si-oxide-nitride-oxide-silicon (SONOS)-type Flash memories on polycrystalline-silicon thin films and found that dangling bonds presented along the grain boundaries in the channel significantly influence their reliability characteristics in the aspects of charge storage, drain disturbance, and gate disturbance. Employing a powerful defect passivation technique, i.e., NH3 plasma treatment, the charge storage capability was clearly observed to be remarkably improved. Even so, the hydrogenated polycrystalline-silicon thin-film transistors (poly-Si-TFTs) still suffered from serious drain and gate disturbances, which exhibited behaviors that are quite specific and undoubtedly distinct from those observed in the conventional SONOS-type memories on single crystalline substrates.
Improving Thermal Stability and Interface State Density of High-kappa Stacks by Incorporating Hf into an Interfacial Layer on p-Germanium
(2016-11)
Tsai, Yi-He
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Chou, Chen-Han
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Shih, An-Shih
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Jau, Yu-Hau
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Yeh, Wen-Kuan
We propose a new HfGeOx interfacial layer (IL) for the high-kappa gate-stacks on p-type germanium substrate with improved thermal stability as compared with that of conventional GeOx IL. We inserted an additional HfO2 layer after the formation of GeOx in the HfO2/Al2O3/GeOx/Ge gate-stack by using plasma-enhanced atomic layer deposition. Through the use of post-deposition annealing and post-metal annealing, the new system exhibited greater thermal immunity and was stable up to 600 degrees C. We speculate that the improvement originates from the formation of HfGeOx through the combination of HfO2 and GeOx, according to the thermodynamic data. By incorporating Hf into interfacial layer, the fabricated high-kappa gate-stack with an equivalent oxide thickness of 1.2 nm, a low interface states density (D-it) of approximately 3.3 x 10(11) eV(-1) cm(-2), and an impressive gate leakage current of approximately 2.2 x 10(-6) A/cm(2) at VFB-1V.
Ion-Bombarded and Plasma-Passivated Charge Storage Layer for SONOS-Type Nonvolatile Memory
(2014-09-01)
Liu, Sheng-Hsien
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Wu, Chi-Chang
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Yang, Wen-Luh
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Lin, Yu-Hsien
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Chao, Tien-Sheng
This paper examined the application of ion bombardment (IB) and NH3 plasma treatment (PT) techniques in fabricating a high-performance Si3N4 charge storage layer. The IB technique can be used for creating numerous additional trap sites in the storage layer to enhance charge trapping efficiency and also causes changes in trap centroid location. In addition, the effect of centroid location on operation efficiency and reliability was investigated. Using gate-sensing and channel-sensing analysis, the changes in centroid location were demonstrated. In addition, the energy-level distribution of trap sites was clearly delineated by performing discharge-based multipulse analysis. The NH3 PT technique can substantially passivate IB-induced shallow trap sites to increase data retention time. The influence of the NH3 PT time on the memory characteristics of an IB-induced Si3N4 sample was investigated. The optimal characteristics of an ion-bombarded and plasma-passivated Si3N4 storage layer are presented. Compared with the conventional Si3N4 storage layer, the optimal ion-bombarded and plasma-passivated Si3N4 sample exhibited higher operation efficiency and superior reliability.
Low-temperature polycrystalline silicon thin-film flash memory with hafnium silicate
(2007-03-01)
Lin, Yu-Hsien
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Chien, Chao-Hsin
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Chou, Tung-Huan
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Chao, Tien-Sheng
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Lei, Tan-Fu
In this paper, we have successfully fabricated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type poly-Si-thin-film transistor (TFT) memories employing hafnium silicate as the trapping layer with low-thermal budget processing (<= 600 degrees C). It was demonstrated that the fabricated memories exhibited good performance in terms of relatively large memory window, high program/erase speed (1 ms/10 ms), long retention time (> 10(6) s for 20% charge loss), and 2-bit operation. Interestingly, we found that these memories depicted very unique disturbance behaviors, which are obviously distinct from those observed in the conventional SONOS-type Flash memories. We thought these specific characteristics are closely related to the presence of the inherent defects along the grain boundaries. Therefore, the elimination of the traps along the grain boundaries in the channel is an important factor for achieving high performance of the SONOS-type poly-Si-TFT Flash memory.
Microwave Annealing for NiSiGe Schottky Junction on SiGe P-Channel
(2015-11-01)
Lin, Yu-Hsien
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Tsai, Yi-He
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Hsu, Chung-Chun
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Luo, Guang-Li
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Lee, Yao-Jen
In this paper, we demonstrated the shallow NiSiGe Schottky junction on the SiGe P-channel by using low-temperature microwave annealing. The NiSiGe/n-Si Schottky junction was formed for the Si-capped/SiGe multi-layer structure on an n-Si substrate (Si/Si0.57Ge0.43/Si) through microwave annealing (MWA) ranging from 200 to 470 degrees C for 150 s in N-2 ambient. MWA has the advantage of being diffusion-less during activation, having a low-temperature process, have a lower junction leakage current, and having low sheet resistance (Rs) and contact resistivity. In our study, a 20 nm NiSiGe Schottky junction was formed by TEM and XRD analysis at MWA 390 degrees C. The NiSiGe/n-Si Schottky junction exhibits the highest forward/reverse current (I-ON/I-OFF) ratio of similar to 3 x 10(5). The low temperature MWA is a very promising thermal process technology for NiSiGe Schottky junction manufacturing.
Nanoscale 2-Bit/Cell HfO2 Nanocrystal Flash Memory
(2012-03-01)
Lin, Yu-Hsien
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Chien, Chao-Hsin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we demonstrate 50-nm trigate nonvolatile HfO2 nanocrystal memory devices on silicon-on-insulator wafers. The proposed technique, which is fully compatible with current CMOS technologies, is used to form highly localized HfO2 nanocrystals for application in nonvolatile flash memory. We successfully scale down conventional nonvolatile floating gate memories below the 50-nm node to achieve nanodevices for application in next-generation nonvolatile memories.
Novel Ion Bombardment Technique for Doping Limited Cu Source in SiOx-Based Nonvolatile Switching Layer
(2013-11-01)
Liu, Sheng-Hsien
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Yang, Wen-Luh
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Lin, Yu-Hsien
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Wu, Chi-Chang
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Chao, Tien-Sheng
A novel ion bombardment (IB) technique is presented to dope a limited Cu source in an SiOx switching layer (SiOx:Cu SL) for nonvolatile memory applications. Compared with other Cu-doping methods, this IB technique has many benefits, including a local-doping effect, room-temperature process, and compatibility with current IC manufacturing technology, besteading the 1T-1R integration. Through transmission electron microscopy and energy dispersive spectrometer analyses, an IB-induced SiOx:Cu SL is confirmed. In contrast with the conventional Cu/SiOx-stacked sample, this IB-induced SiOx:Cu SL exhibits superior performance in terms of lower forming/RESET voltages, higher uniformity of SET/RESET voltages, and more stable high-temperature retention characteristics. Additionally, so far, this IB-induced TaN/SiOx:Cu/TaN device has shown the best switching endurance properties for the general SiOx-based Cu filament resistance random access memory.
Switching characteristics in Cu:SiO2 by chemical soak methods for resistive random access memory (ReRAM)
(2015-01-01)
Chin, Fun-Tat
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Lin, Yu-Hsien
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Yang, Wen-Luh
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Liao, Chin-Hsuan
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Lin, Li-Min
A limited copper (Cu)-source Cu:SiO2 switching layer composed of various Cu concentrations was fabricated using a chemical soaking (CS) technique. The switching layer was then studied for developing applications in resistive random access memory (ReRAM) devices. Observing the resistive switching mechanism exhibited by all the samples suggested that Cu conductive filaments formed and ruptured during the set/reset process. The experimental results indicated that the endurance property failure that occurred was related to the joule heating effect. Moreover, the endurance switching cycle increased as the Cu concentration decreased. In high-temperature tests, the samples demonstrated that the operating (set/reset) voltages decreased as the temperature increased, and an Arrhenius plot was used to calculate the activation energy of the set/reset process. In addition, the samples demonstrated stable data retention properties when baked at 85 degrees C, but the samples with low Cu concentrations exhibited short retention times in the low-resistance state (LRS) during 125 degrees C tests. Therefore, Cu concentration is a crucial factor in the trade-off between the endurance and retention properties; furthermore, the Cu concentration can be easily modulated using this CS technique. (C) 2014 Elsevier Ltd. All rights reserved.
Two-bit lanthanum oxide trapping layer nonvolatile flash memory
(2007)
Lin, Yu-Hsien
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Chien, Chao-Hsin
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Yang, Tsung-Yuan
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Lei, Tan-Fu
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電子工程學系及電子研究所
This paper describes the two-bit characteristics of SONOS-type memories prepared using lanthanum oxide, a high-k dielectric material, as the trapping layers. We used "channel hot-electron injection" for programming and "band-to-band hot-hole injection" for erasing to perform the memory operations. We observed large memory windows, a relatively high P/E speed, and good retention characteristics for these SONOS-type memories. It appears that La2O3 is an excellent candidate for use as the trapping layer in SONOS-type memories. (C) 2007 The Electrochemical Society.
Two-bit/four-level Pr2O3 trapping layer for silicon-oxide-nitride-oxide-silicon-type flash memory
(2012-01-01)
Lin, Yu-Hsien
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You, Hsin-Chiang
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Chien, Chao-Hsin
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This study proposes and demonstrates a silicon-oxide-nitride-oxide-silicon (SONOS)-type memory device based on a high-k dielectric praseodymium oxide (Pr2O3) trapping layer. In the proposed design, channel hot electron injection programming and band-to-band hot-hole injection erasing allow highly efficient two-bit and four-level device operation. The proposed design also has a total memory window of 5 V, a ten-year V-t retention window larger than 0.8 V between adjacent levels, and enough memory window for 10(5) programming/erasing cycles of endurance. The proposed SONOS-type Pr2O3 trapping layer flash memory exhibits large memory windows, high program/erase speed, good endurance, and good disturbance characteristics. (C) 2012 American Vacuum Society. [DOI: 10.1116/1.3668101]