Browsing by Author "Liou, Guan-Lin"

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Energy-Efficient Versatile Memories With Ferroelectric Negative Capacitance by Gate-Strain Enhancement
(2017-08-01)
Chiu, Yu-Chien
;
Cheng, Chun-Hu
;
Liou, Guan-Lin
;
Chang, Chun-Yen
;
電子工程學系及電子研究所
In this brief, we reported a ferroelectric versatile memory with strained-gate engineering. The versatile memory with high-strain-gate showed a >40% improvement on ferroelectric hysteresis window, compared to low-strain case. The high compressive stress induced from high nitrogen-content TaN enhances monoclinic-to-orthorhombic phase transition to reach stronger ferrolectric polarization and lower depolarization field. The versatile memory featuring ferroelectric negative capacitance exhibited excellent transfer characteristics of the sub-60-mVdec subthreshold swing, ultralow off-state leakage of <1fA/mu m and > 108 on/off current ratio. Furthermore, the ferroelectric versatile memory can be switched by +/- 5 V under 20-ns speed for a long endurance cycling (similar to 10(12) cycles). The low-power operation can be ascribed to the amplification of the surface potential to reach the strong inversion and fast domain polarization at the correspondingly low program/erase voltages.
Experimental Observation of Negative Capacitance Switching Behavior in One-Transistor Ferroelectric Versatile Memory
(2017-10-01)
Cheng, Chun-Hu
;
Chiu, Yu-Chien
;
Liou, Guan-Lin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, we investigated the negative capacitance behavior of novel ferroelectric versatile memory with low-voltage-driven and fast ferroelectric switching. The combined storage mechanism strengthened the stability of ferroelectric polarization by interface aligned dipoles. The simulation results of first principle calculation indicated that the monoclinic-like orthorhombic phase of ferroelectric hafnium oxide facilitated the occurrence of S-shaped negative capacitance behavior. Furthermore, the control of phase transition may affect ferroelectric property and negative capacitance effect during program and erase states.
Fast Low-Temperature Plasma Process for the Application of Flexible Tin-Oxide-Channel Thin Film Transistors
(2017-09-01)
Chen, Po-Chun
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Chiu, Yu-Chien
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Zheng, Zhi-Wei
;
Lin, Ming-Huei
;
Cheng, Chun-Hu
In this study, we demonstrated a p-type and n-type SnO TFTs on flexible polyimide substrate. The fabricated p-type SnO TFT showed a high I-on/I-off of 5.7 x 10(5) and a high mu(FE) of 10.7 cm(2) V-1 s(-1). Through optimizing the oxygen plasma condition, the n-type channel TFT transfered from prime p-type channel exhibits excellent characteristics, including a high on/off current ratio of 6.6 x 10(3), a low threshold voltage of -0.13 V, and a very high field-effect mobility of 28 cm(2) V-1 s(-1). This proposed low-temperature oxygen plasma treatment shows the potential in simplification of TFT process that can achieve n-type and p-type TFTs under the same device process.
Impact of Ferroelectric Domain Switching in Nonvolatile Charge-Trapping Memory
(2017-01-01)
Fan, Chia-Chi
;
Chiu, Yu-Chien
;
Liu, Chien
;
Liou, Guan-Lin
;
Lai, Wen-Wei
In this work, we proposal a ferroelectric domain to enhance program/erase/read efficiency of conventional charge-trapping nonvolatile memory. The ferroelectric-domain-dominated HfZrO/HfON memory shows the better subthreshold characteristics than control charge-trapping structure (HfO2/HfON). Additionally, the memory speed with ferroelectric polarization (similar to 800ns) is more than three orders of magnitude faster than that of control trapping type.
Improved Electrical Characteristics and Reliability of Multi-Stacking PNPN Junctionless Transistors Using Channel Depletion Effect
(2017-01-01)
Lin, Ming-Huei
;
Shih, Yi-Jia
;
Liu, Chien
;
Chiu, Yu-Chien
;
Fan, Chia-Chi
This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >10(7). Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.
Interface Engineering of Ferroelectric Negative Capacitance FET for Hysteresis-Free Switch and Reliability Improvement
(2018-01-01)
Fan, Chia-Chi
;
Tu, Chun-Yuan
;
Lin, Ming-Huei
;
Chang, Chun-Yen
;
Cheng, Chun-Hu
In this work, we successfully achieve a hysteresis-free negative capacitance field effect transistors (NCFETs) by exploiting a defect passivation scheme. This research work simultaneously provides a new insight into the gate-oxide stress reliability of NCFET. The fluorine-passivated HfAlOx NCFET shows the excellent transistor characteristics including a steep subthreshold swing of sub-30-mV/dec, a negligible hysteresis-free switch of similar to 10mV and a large on/off current reatio (I-on/I-off) of >10(7). Most importantly, fluorine passivation for NC HfAlOx effectively suppress the generation of shallow traps during electrical stress test. Besides, it is favorable to maintain NC operation and SILC immunity by in-situ fluorine passivation, which has been verified by transient pulse I-V measurement.
On the Variability of Threshold Voltage Window in Gate-Injection Versatile Memories with Sub-60mV/dec Subthreshold Swing and 10(12)-Cycling Endurance
(2016)
Chiu, Yu-Chien
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Chang, Chun-Yen
;
Yen, Shiang-Shiou
;
Fan, Chia-Chi
;
Hsu, Hsiao-Hsuan
Incorporating a charge-trapped ZrSiO with ferroelectric HfZrO dielectrics, we demonstrated a gate-injection versatile memory with sub-60mV/dec subthreshold swing (SS) and large threshold voltage window (Delta V-T) of >2V under a fast 20-ns speed. Moreover, it is revealed that the local defects at ZrSiO/HfZrO interface affect the ferroelectric negative capacitance tuning and thus increases the variability of V-T and SS during 10(12) cycling endurance.
Performance Enhancements in p-Type Al-Doped Tin-Oxide Thin Film Transistors by Using Fluorine Plasma Treatment
(2017-02)
Chen, Po-Chun
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Chiu, Yu-Chien
;
Liou, Guan-Lin
;
Zheng, Zhi-Wei
;
Cheng, Chun-Hu
This letter reports on a tin oxide (SnO) thin-film transistor (TFT) with p-type conduction that uses aluminum (Al) doping in the SnO active channel layer. Performance enhancements were further achieved by applying fluorine plasma treatment on the p-type Al-dopedSnO channel layer. The effects of the fluorine plasma treatment were also investigated. By tuning the power of the fluorine plasma treatment on the p-type Al-doped SnO channel layer, the optimal TFT device showed a very high on/off current ratio of 2.58x10(6) and a low threshold swing of 174 mV/decade, which could be attributed to the passivation effect of the plasma fluorination on the dominant donor-like traps at the SnO/HfO2 interface, as reflected by the suppression of the hysteresis phenomenon, the low density of interface traps, and the small subthreshold swing. The results indicate that the p-type Al-doped SnO TFT device with fluorine plasma treatment has considerable potential for application in future high-performance displays.
Photocapacitive Effect of Ferroelectric Hafnium-Zirconate Capacitor Structure
(2017-01-01)
Liou, Guan-Lin
;
Cheng, Chun-Hu
;
Chiu, Yu-Chien
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, we investigated the photocapacitive effect of the metal-ferroelectric-insulator-semiconductor capacitors under illumination. The photocapacitive effect is mainly caused by light photon excitation, contributed from the variation of depletion charge. We suggested that the ferroelectric domains are affected by defect dipole charges formed by the interface trapped charges to lead to the variation of depletion capacitance.
Program/Erase Speed and Data Retention Trade-Off in Negative Capacitance Versatile Memory
(2017-01-01)
Fan, Chia-Chi
;
Chiu, Yu-Chien
;
Liu, Chien
;
Liou, Guan-Lin
;
Lai, Wen-Wei
In this work, we investigated the performance tradeoff between program/erase speed and data retention of ferroelectric HfZrO memory. The monoclinic HfNO layer with a trapping mechanism was employed to improve the data retention. Under the thickness optimization of HfNO, the HfZrO/HfNO gate stack can be functionalized with volatile and non-volatile operation.