Improved Electrical Characteristics and Reliability of Multi-Stacking PNPN Junctionless Transistors Using Channel Depletion Effect

Abstract

This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >10(7). Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.