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Improved Electrical Characteristics and Reliability of Multi-Stacking PNPN Junctionless Transistors Using Channel Depletion Effect

dc.citation.epage48en_US
dc.citation.spage47en_US
dc.contributor.authorLin, Ming-Hueien_US
dc.contributor.authorShih, Yi-Jiaen_US
dc.contributor.authorLiu, Chienen_US
dc.contributor.authorChiu, Yu-Chienen_US
dc.contributor.authorFan, Chia-Chien_US
dc.contributor.authorLiou, Guan-Linen_US
dc.contributor.authorCheng, Chun-Huen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2018-08-21T05:57:00Z
dc.date.available2018-08-21T05:57:00Z
dc.date.issued2017-01-01en_US
dc.description.abstractThis work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >10(7). Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.en_US
dc.identifier.issn2161-4636en_US
dc.identifier.journal2017 SILICON NANOELECTRONICS WORKSHOP (SNW)en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/146934
dc.identifier.wosnumberWOS:000425209200024en_US
dc.language.isoen_USen_US
dc.titleImproved Electrical Characteristics and Reliability of Multi-Stacking PNPN Junctionless Transistors Using Channel Depletion Effecten_US
dc.typeProceedings Paperen_US

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