Browsing by Author "Liu, Chien-Nan"

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A Scalable Digitalized Buffer for Gigabit I/O
(2008)
Lu, HungWen
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Su, ChauChin
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Liu, Chien-Nan
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交大名義發表
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National Chiao Tung University
A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18 mu m CMOS process, the I/O occupies an area of 0.014mm(2) and operates from 4Gbps@1.9V to 1.5Gbps@1.1V.
Analog Placement with Current Flow and Symmetry Constraints using PCP-SP
(2018-01-01)
Patyal, Abhishek
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Pan, Po-Cheng
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Asha, K. A.
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Chen, Hung-Ming
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Chi, Hao-Yu
Modern analog placement techniques require consideration of current path and symmetry constraints. The symmetry pairs can be efficiently packed using the symmetry island configurations, but not all these configurations result in minimum gate interconnection, which can impact the overall circuit routing and performance. This paper proposes the first work that reformulates this problem considering all of them together in the form of Parallel Current Path (PCP) constraints. Then a placement algorithm satisfying these constraints is formulated to reduce a vast search space via efficient sequence pair manipulation. Experimental results show that this formulation and algorithm can satisfy all the constraints in a more tightly packed configuration, resulting in lesser routing length, reduced parasitics and thus better post-layout performance.
Using power gating techniques in area-array SoC floorplan design
(2007-01-01)
Yeh, Chi-Yi
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Chen, Hung-Ming
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Huang, Li-Da
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Wei, Wei-Ting
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Lu, Chao-Hung
Low power demand drives the development of lower power design architectures, among which power gating is one of the state-of-the-art techniques to achieve low power. NITCMOS (or sleep transistor) is applied when some of the blocks can be switched off without leakage power dissipation. This technique is widely used in circuit level design, but hardly used in higher level design stage. Due to early planning in power delivery for area-array design style, it is necessary to consider the power gating techniques in early SoC physical design stage. This paper presents a framework to insert coarse grain MTCMOS in SoC floorplanning stage, saving mainly leakage power. This work decides which modules have chance to save power by sleep transistors insertion, and reserves enough area for them during floorplarming. The results show that our approach works well and can obtain lower power floorplans with supply noise aware sleep transistor insertion in area-array architecture.