A Scalable Digitalized Buffer for Gigabit I/O
Loading...
Date
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
DOI
10.1109/CICC.2008.4672068
Abstract
A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18 mu m CMOS process, the I/O occupies an area of 0.014mm(2) and operates from 4Gbps@1.9V to 1.5Gbps@1.1V.