Browsing by Author "Liu, Chien-Nan Jimmy"

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A Structure-Based Methodology for Analog Layout Generation
(2019-01-01)
Chen, Yu-Hsien
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Chi, Hao-Yu
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Song, Ling-Yen
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Liu, Chien-Nan Jimmy
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Chen, Hung-Ming
In order to speed up analog design cycles, analog layout automation is a popular research in recent years. However, most previous works assume that the required design constraints are given by users manually. Designers still take a lot of time to fill-in the required design information. Template-based layout generation is another approach to consider the design constraints, but considerable development efforts are required for each new design and each new technology. In this paper, we propose a structure-based methodology for analog layout generation. This methodology starts from a structure analysis that divides the circuit netlist into several building blocks automatically. It can help to reduce the dependence on users' input and generate corresponding design constraints for the succeeding layout steps. With the help from structure analysis, the layouts of those analog structures are generated, placed, and routed automatically with proper constraints. As shown in the demo cases, the proposed flow is able to generate the required layout accurately without users' intervention and still keeps the post-layout performance within specifications.
A tableless approach for high-level power modeling using neural networks
(2007-01-01)
Hsu, Chih-Yang
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Hsieh, Wen-Tsan
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Liu, Chien-Nan Jimmy
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Jou, Jing-Yang
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電子工程學系及電子研究所
For complex digital circuits, building their power models is a popular approach to estimate their power consumption without detailed circuit information. In the literature, most of power models have to increase their complexity in order to meet the accuracy requirement. In this paper, we propose a tableless power model for complex circuits that uses neural networks to learn the relationship between power dissipation and input/output signal statistics. The complexity of our neural power model has almost no relationship with circuit size and number of inputs and outputs such that this power model can be kept very small even for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear characteristic of power distributions and the effects of both state-dependent leakage power and transition-dependent switching power. The experimental results have shown the accuracy and efficiency of our approach on benchmark circuits and one practical design for different test sequences with wide range of input distributions.
A Tree-Topology Multiplexer for Multiphase Clock System
(2009-01-01)
Lu, Hungwen
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Su, Chauchin
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Liu, Chien-Nan Jimmy
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電控工程研究所
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Institute of Electrical and Control Engineering
This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show g that the proposed design can achieve higher bandwidth and be less ss sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- mu m CMOS technology. Measured results indicate that the proposed design can operate tip to 7 gigabits/s under 0.3-Ul jitter limitation.
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging
(2009-02-01)
Jiang, Tai-Ying
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Liu, Chien-Nan Jimmy
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Jou, Jing-Yang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
When hardware description languages (HDLs) are used in describing the behavior of a digital circuit, design errors (or bugs) almost inevitably appear in the HDL code of the circuit. Existing approaches attempt to reduce efforts involved in this debugging process by extracting a reduced set of error candidates. However, the derived set can still contain many error candidates, and finding true design errors among the candidates in the set may still consume much valuable time. A debugging priority method [21] was proposed to speed up the error-searching process in the derived error candidate set. The idea is to display error candidates in an order that corresponds to an individual's degree of suspicion. With this method, error candidates are placed in a rank order based on their probability of being an error. The more likely an error candidate is, a design error (or a bug), the higher the rank order that it has. With the displayed rank order, circuit designers should find design errors quicker than with blind searching when searching for design errors among all the derived candidates. However, the currently used confidence score (CS) for deriving the debugging priority has some flaws in estimating the likelihood of correctness of error candidates due to the masking error situation. This reduces the degree of accuracy in establishing a debugging priority. Therefore, the objective of this work is to develop a new probabilistic confidence score (PCS) that takes the masking error situation into consideration in order to provide a more reliable and accurate debugging priority. The experimental results show that our proposed PCS achieves better results in estimating the likelihood of correctness and can indeed suggest a debugging priority with better accuracy, as compared to the CS.
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines
(2019-01-01)
Chi, Hao-Yu
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Lin, Zi-Jun
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Hung, Chia-Hao
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Liu, Chien-Nan Jimmy
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Chen, Hung-Ming
In order to improve design productivity, proper layout automation tools are desired for analog circuits. Layout migration is one possible approach to generate a new layout for given circuits with different device sizes or different technology, and still keep the original layout topology. However, routing behaviors are often not mentioned in previous works, which requires a complete rerouting that may not follow the original style. Pan [16] first proposed a Constrained Delaunay Triangulation (CDT) based model to keep the routing behavior during layout migration. However, because the device sizes and related distance may be different in the new layout, some reference lines in CDT models may be removed, resulting in some missing nets after migration. In this paper, a novel Cartesian Detection Line (CDL) based model is proposed to preserve the routing behavior in original layouts. Because alternative lines in the modified placement can be easily found to prevent from missing nets, the proposed CDL model greatly improves the routing completeness during layout migration. Several routing refinement techniques are also proposed to solve the routing issues due to block displacement. In our experiments, the routing completeness can be improved to almost 100% with the proposed CDL model, which greatly reduces the design efforts.
Adaptive Two-Stage Fuzzy Temperature Control for an Electroheat System
(2009-03-01)
Wang, Chih-Hu
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Lin, Chun-Hung
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Lee, Bore-Kuen
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Liu, Chien-Nan Jimmy
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Su, Chauchin
In this paper, we construct a simple adaptive two-stage fuzzy temperature tracking controller for a commercial electroheat system. Being not well isolated from the environment, it is hard to build an analytical model for the system due to heat convection caused by a fan for heat mixing in the chamber, heat leakage to the environment, variation of the environment temperature, and uncertain nonlinear heating dynamics. Also, as a commercial product by using cheap heater coils and without equipping a cooling system, this system usually has a bad transient response such as a long rise time, a large overshoot, and a long settling time. Moreover, temperature tracking at the steady-state phase is not easy to maintain due to heat interaction with the environment. Here, in the presence of the unknown system dynamics, we use a two-stage fuzzy controller to improve the transient response. Furthermore, a simple fine-tuning adaptive control scheme is proposed to overcome environmental influence and ensure tracking of the temperature setting. Simulation study and experimental results show good performance of the adaptive fuzzy temperature control system.
An effective decap insertion method considering power supply noise during floorplanning
(2008-01-01)
Lu, Chao-Hung
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Chen, Hung-Ming
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Liu, Chien-Nan Jimmy
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
As VLSI technology enters the nanometer era, the supply voltage is continually dropped. This condition helps to reduce the power dissipation, but make the power integrity problem become worse. Employing decoupling capacitances (decap) at floorplan stage has been a common approach to alleviate the supply noise problem. However, the decap budget is often overly estimated in previous researches. Besides the decap budget computation, the available floorplan space does not fully used in previous works. In one floorplan, it usually has many available spaces except the empty space that could be used to insert the decap without increasing the floorplan area. Therefore, our goal in this work is to develop a better model to calculate the required decap to solve the power supply noise problem of area-array based designs and to increase he usage of the available space in the floorplan to reduce the area overhead caused by decap insertion. The experimental results are encouraging. Compared with other approaches, our algorithm can reduce 52.6% decap budget on the MCNC benchmarks but still keep the power supply noise in the given constraint. The final floorplan areas with decap are also less than the numbers reported in previous papers.
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness
(2005)
Jiang, Tai-Ying
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Liu, Chien-Nan Jimmy
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Jou, Jing-Yang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Simulation based validation approaches are still the primary workhorse for solving the verification problem of getting the initial HDL description correct, especially for large scaled designs. However, most of existing code coverage metrics do not address obsevability issue [2]. Therefore, we intend to provide additional observability measures to statement coverage metric for more proper and realistic evaluation of verification completeness for a HDL design. As compared to OCCOM [1,2,3], our approach estimates a real probabilistic likelihood of propagating erroneous effects without any unreasonable assumptions and can always provide lower bound estimation.
Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System
(2009-11-01)
Tseng, Yuhwai
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Su, Chauchin
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Liu, Chien-Nan Jimmy
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電控工程研究所
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Institute of Electrical and Control Engineering
This study develops a form of digital baseband Intra-Body communication for wideband transmission. A simplified circuit model of signal and noise is constructed to analyze the contribution of the high pass filter function of the electrostatic coupling Intra-Body communication system to wideband digital transmission in electrostatic coupling Intra-Body communication. A unit step function is presented to determine the maximum high pass 3 dB pole that can ensure favorable signal quality in a baseband Intra-Body communication system. Body noise is measured to estimate the range of the high pass 3dB pole with good Signal to Noise Ratio. A 3.3 Volt battery-powered FPGA is experimentally implemented to confirm the feasibility of the wideband Intra-Body communication system. The experimental results indicate that the digital baseband Intra-Body communication system supports a data rate of more than 16MPS.
Design of an All-Digital LVDS Driver
(2009-08-01)
Lu, Hungwen
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Wang, Hsin-Wen
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Su, Chauchin
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Liu, Chien-Nan Jimmy
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電控工程研究所
This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-mu m 1P6M CMOS process with a core area of 0.072 mm(2). At 3 Gbps, it consumes 9 mW of power under a 1.8-V power supply or 3 pJ/bit.
Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits
(2011-01-01)
Lu, Chao-Hung
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Chen, Hung-Ming
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Liu, Chien-Nan Jimmy
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Billions of transistors are placed in one single chip (SoC) with advanced manufacturing technology. Further development is obstructed by the ability to the manufacture of SoC and the signal integrity. Stacking IC is an alternative choice when we design a high-performance high-density chip. Design flow (especially physical design) is facing different issues when compared with 2D IC design. The location of the I/Os seriously affect the number of 3D-Vias and their total area in the stacking IC. This paper proposes a Stacking IC architecture and the corresponding design flow to solve the I/O and 3D-Via problems. In this flow, we have developed a system partition approach to minimize the number of 3D-Vias and balance the I/O number of each tier, and modified one traditional floorplan method to optimize the I/O and module locations. The experimental results are encouraging in the GSRC benchmarks. Compared with greedy and intuitive methods, our framework reduces the number of 3D-Vias by 30.02% on the average and can balance the I/O count of each tier. The dead space of the final floorplan is reduced by 14.13%.
Effective Decap Insertion in Area-Array SoC Floorplan Design
(2008-09-01)
Lu, Chao-Hung
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Chen, Hung-Ming
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Liu, Chien-Nan Jimmy
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
As VLSI technology enters the nanometer era, supply voltages continue to drop due to the reduction of power dissipation, but it makes power integrity problems even worse. Employing decoupling capacitances (decaps) in floorplan stage is a common approach to alleviating supply noise problems. Previous researches overestimate the decap budget and do not fully utilize the empty space of the floorplan. A floorplan usually has a lot of available space that can be used to insert the decap without increasing the floorplan area. Therefore, the goal of this work is to develop a better model to calculate the required decap to solve the power supply noise problem in area-array based designs, and increase the usage of available space in the floorplan to reduce the area overhead caused by decap insertion. The experimental results of this work are encouraging. Compared with previous approaches, our methodology reduces 38% of the decap budget in average for MCNC benchmarks but can still meet the power supply noise requirements. The final floorplan areas with decap are also smaller than the numbers reported in previous works.
Estimation of loss coefficients of Nonlinear rubber using iterative H-infinity filter
(2006-01-01)
Chih-Hu Wang
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Lee, Bore-Kuen
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Wei-Hang Tseng
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Chung-Hsi Fu
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Chauchin Su
For automobile industry, rubber is widely used for noise isolation and vibration reduction. However, due to its distributed and nonlinear characteristics, it is hard to precisely estimate its characteristics such as the loss coefficient which is defined as the tangent of the phase delay between the fundamental components of the strain and the stress under sinusoidal driving. Moreover, even using a truncated finite-dimensional model, with rubber's nonlinearity, resonance of the testing mechanical system, and measurement noise, optimal estimation of the loss coefficient by using Kalman filter is not feasible in the presence of these uncertainties and non-Gaussian disturbances. Therefore, H-infinity filter is applied in this paper to robustly estimate the loss coefficient from the state-space perspective. As a state-space model for representing a sinusoidal signal has eigenvalues on the unit circle, the measured data is first processed by imposing a suitable exponential decay in order to ensure the stability of the H-infinity filter. Moreover, due to finite data length, an iterative H-infinity filter is developed to improve the accuracy of parameter estimates. At each iteration, estimation of disturbances by using the H-infinity filter is first performed by applying the previously estimated components of the desired signal. Then a robust estimation of the desired signal is made with respect to the measured signal which is subtracted by the estimated disturbance. Both simulation study and experimental test are conducted to verify the performance of the proposed iterative H. filter.
H-infinity output feedback control of stochastic T-S fuzzy model with state-dependent noise
(2008-01-01)
Ho, Shih-Ju
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Wang, Chih-Hu
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Lee, Bore-Kuen
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Su, Chauchin
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Liu, Chien-Nan Jimmy
Estimator which guarantee H-infinity robustness performance for the considered nonlinear stochastic systems can be obtained by solving bilinear matrix inequalities. Then, to solve the bilinear matrix inequalities, a two-stage method is adopted to separately obtain the controller gain matrices and the eatimator gain matrices by solving two sets of linear matrix inequalities. An example is given to verify the derived results.
Long-Range Prediction for Real.-Time MPEG Video Traffic: An H(infinity) Filter Approach
(2008-12-01)
Wang, Chih-Hu
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Chen, Bor-Sen
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Lee, Bore-Kuen
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Lee, Tsu-Tian
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Liu, Chien-Nan Jimmy
A novel prediction scheme is proposed for real-time MPEG video to predict the burst and long-range dependent traffic. The trend and periodic characteristics of MPEG video traffic are fully captured by a proposed stochastic state-space dynamic model. Then a recursive H. filtering algorithm is proposed to estimate traffic for long-range prediction. Simulation results based on real MPEG traffic data show that the proposed scheme has superior performance and lower complexity than some adaptive neural network methods, such as TDNN, NARX, and Elman neural networks.
Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave
(2010-06-01)
Tseng, Yuhwai
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Su, Chauchin
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Liu, Chien-Nan Jimmy
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電控工程研究所
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Institute of Electrical and Control Engineering
In this study, we use the deconvolution of a square test stimulus to replace a series of sinusoidal test waveforms with different frequencies to simplify the measurement of human body impedance. The average biological impedance of body parts is evaluated by constructing a frequency response of the equivalent human body system. Only two stainless-steel electrodes are employed in the measurement and evaluation.
Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus
(2010-03-01)
Tseng, Yuhwai
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Su, Chauchin
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Liu, Chien-Nan Jimmy
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電控工程研究所
;
Institute of Electrical and Control Engineering
This study employs a simple measurement methodology that is based on the de-convolution of a square test stimulus to measure the transmission characteristics of the human body channel in an electrostatic-coupling intra body communication system. A battery-powered square waveform generator was developed to mimic the electrostatic-coupling intra body communication system operating in the environment of the ground free. The measurement results are then confirmed using a reliable measuring method (single tone) and spectral analysis. The results demonstrate that the proposed measurement approach is valid for up to 32.5 MHz, providing a data rate of over 16 Mbps.
Observability analysis on HDL descriptions for effective functional validation
(2007-08-01)
Jiang, Tai-Ying
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Liu, Chien-Nan Jimmy
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Jou, Jing-Yang
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Simulation-based functional validation is still one of the primary approaches for verifying designs described in hardware description languages. Traditional code coverage metrics do not address the observability issue and may overestimate the extent of functional validation. Observability-based code coverage metric (OCCOM) is the first code coverage metric considering the essential observability issue. However, tags can only be observed or unobserved, providing only two levels of measurement (i.e., 1 and 0). Errors with lower opportunities to be observed may still be judged as observable, thus misleading the verification results. Therefore, instead of extending tag coverage, we develop a probabilistic observability measure and its efficient computation algorithm. Besides being used as a new OCCOM, our new measure can point out hard-to-observe points for inserting assertions to prevent bugs from hiding behind these points. Experimental results show that the detection of the injected errors and the degree of our observability measure are strongly related. The results also show that our fine-grained observability measure is less likely to overestimate the extent of validation. with reasonable computation time.
On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design
(2007)
Lu, Chao-Hung
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Chen, Hung-Ming
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Liu, Chien-Nan Jimmy
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-drop and simultaneous switching noise, and decoupling capacitance (decap) insertion is commonly applied to alleviate the noise. There exist some approaches to addressing this issue, but they suffer either from over-design problem or late decap insertion during design stage. In this paper, we propose a methodology to insert decap in a more efficient and effective way during early design stage in area-array designs. The experimental results are encouraging. Compared with other approaches in [15] and [12], we have inserted enough decap to meet supply noise constraint while others employ more area.
Package Routability- and IR-Drop-Aware Finger/Pad Assignment in Chip-Package Co-Design
(2009)
Lu, Chao-Hung
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Chen, Hung-Ming
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Liu, Chien-Nan Jimmy
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Shih, Wen-Yu
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電子工程學系及電子研究所
Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations affect the performance of the chip and the package significantly. In this paper, we have. developed techniques in chip-package codesign to decide the locations of fingers/pads for package routability and signal integrity concerns in chip core design. Our finger/pad assignment is a two-step method: first we optimize the wire congestion problem in package routing, and then we try to minimize the IR-drop violation with finger/pad solution refinement The experimental results are encouraging. Compared with the randomly optimized methods, our approaches reduce in average 42% and 68% of the maximum density in package and 10.61% of IR-drop for test circuits.