A Tree-Topology Multiplexer for Multiphase Clock System

Abstract

This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show g that the proposed design can achieve higher bandwidth and be less ss sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- mu m CMOS technology. Measured results indicate that the proposed design can operate tip to 7 gigabits/s under 0.3-Ul jitter limitation.