Browsing by Author "Liu, Jen-Chieh"

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A 8 Phases 192 MHz Crystal-Less Clock Generator with PVT Calibration
(2017-01)
Lu, Ting-Chou
;
Ker, Ming-Dou
;
Zan, Hsiao-Wen
;
Liu, Jen-Chieh
;
Lee, Yu
A multi-phase crystal-less clock generator (MPCLCG) with a process-voltage-temperature (PVT) calibration circuit is proposed. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18pm CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65 mu m x 75 mu m and consumes 1.1 mW with the power supply of 1.8 V. Temperature coefficient (TC) is 69.5 ppm/degrees C from 0 to 100 degrees C, and 2-point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58-ps RMS jitter and a 34.55-ps peak-to-peak jitter (P2P jitter) at 192 MHz within 12.67k-hits. At 192 MHz, it shows a 1-MHz-offset phase noise of -102 dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3%, respectively.
A 8 Phases 192 MHz Crystal-Less Clock Generator with PVT Calibration
(2017-01)
Lu, Ting-Chou
;
Ker, Ming-Dou
;
Zan, Hsiao-Wen
;
Liu, Jen-Chieh
;
Lee, Yu
A multi-phase crystal-less clock generator (MPCLCG) with a process-voltage-temperature (PVT) calibration circuit is proposed. It operates at 192 MHz with 8 phases outputs, and is implemented as a 0.18pm CMOS process for digital power management systems. A temperature calibrated circuit is proposed to align operational frequency under process and supply voltage variations. It occupies an area of 65 mu m x 75 mu m and consumes 1.1 mW with the power supply of 1.8 V. Temperature coefficient (TC) is 69.5 ppm/degrees C from 0 to 100 degrees C, and 2-point calibration is applied to calibrate PVT variation. The measured period jitter is a 4.58-ps RMS jitter and a 34.55-ps peak-to-peak jitter (P2P jitter) at 192 MHz within 12.67k-hits. At 192 MHz, it shows a 1-MHz-offset phase noise of -102 dBc/Hz. Phase to phase errors and duty cycle errors are less than 5.5% and 4.3%, respectively.
AC stress and electronic effects on SET switching of HfO2 RRAM
(2017-08-28)
Liu, Jen-Chieh
;
Magyari-Kope, Blanka
;
Qin, Shengjun
;
Zheng, Xin
;
Wong, H. -S. Philip
An AC stress test was performed to investigate the accompanying electronic effects in a HfO2 resistive random access memory during the SET transition, which featured a sudden decrease in resistance. Comparing the DC and AC measurement results indicated the pronounced influence of interrupted stress on both the mean values and variations of time to SET. First-principles calculations suggested that the charge states (+2, +1, or neutral) of oxygen vacancies affect the migration barrier for forming oxygen vacancy clusters. Therefore, a charge-state-dependent SET model is proposed to include the additional electronic effects induced by the dynamics of electron trapping and detrapping in oxygen vacancies during AC stress. A trimodal Weibull fitting based on the proposed model reproduced the experimental time to SET distributions obtained in a wide range of AC stress conditions. Published by AIP Publishing.
All Digital Phase-Locked Loop Using Active Inductor Oscillator and Novel Locking Algorithm
(2011)
Huang, Tzu-Chi
;
Huang, Hong-Yi
;
Liu, Jen-Chieh
;
Cheng, Kuo-Hsing
;
Luo, Ching-Hsing
A fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390x390 um(2). The power consumption is 5.4 mW at 416 MHz.
Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example
(2015-08-01)
Liu, Jen-Chieh
;
Hsu, Chung-Wei
;
Wang, I-Ting
;
Hou, Tuo-Hung
;
電子工程學系及電子研究所
This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM.
Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
(2017-01-01)
Chang, Chih-Cheng
;
Liu, Jen-Chieh
;
Shen, Yu-Lin
;
Chou, Teyuh
;
Chen, Pin-Chun
This paper highlights the feasible routes of using resistive memory (RRAM) for accelerating online training of deep neural networks (DNNs). A high degree of asymmetric nonlinearity in analog RRAMs could be tolerated when weight update algorithms are optimized with reduced training noise. Hybrid-weight Net (HW-Net), a modified multilayer perceptron (MLP) algorithm that utilizes hybrid internal analog and external binary weights is also proposed. Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.
Investigating MLC Variation of Filamentary and Non-filamentary RRAM
(2014-01-01)
Liu, Jen-Chieh
;
Wang, I-Ting
;
Hsu, Chung-Wei
;
Luo, Wun-Cheng
;
Hou, Tuo-Hung
Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design
(2018-05-01)
Liu, Jen-Chieh
;
Wu, Tzu-Yun
;
Hou, Tuo-Hung
;
電機學院
;
College of Electrical and Computer Engineering
A device-circuit co-design strategy of incremental step pulse programming (ISPP) tailored specifically for resistive-switching random access memory (RRAM) is elaborated using HfO2 RRAM as an example. The proposed strategy optimizes ISPP by considering programming energy, speed, peripheral circuit design, and device lifetime simultaneously. Interplay between ISPP configuration and device switching behavior is comprehensively clarified, and the result provides useful indicators for estimating peripheral circuit overhead and programming performance. Overstress effects affect both switching voltages and endurance lifetime substantially and, thus, should be carefully minimized.
RRAM SET Speed-Disturb Dilemma and Rapid Statistical Prediction Methodology
(2012)
Luo, Wun-Cheng
;
Liu, Jen-Chieh
;
Feng, Hsien-Tsung
;
Lin, Yen-Chuan
;
Huang, Jiun-Jia
This paper presents a first comprehensive study of SET speed-disturb dilemma in RRAM using statistically-based prediction methodologies. A rapid ramped-voltage stress based on percolation model and power-law V-t dependence showed excellent agreement with the time-consuming constant-voltage stress, and was applied to evaluate current status of RRAM devices in the literature.
Statistical Model and Rapid Prediction of RRAM SET Speed-Disturb Dilemma
(2013-11-01)
Luo, Wun-Cheng
;
Liu, Jen-Chieh
;
Lin, Yen-Chuan
;
Lo, Chun-Li
;
Huang, Jiun-Jia
A comprehensive study of SET speed-disturb dilemma in resistive-switching random access memory (RRAM) is presented using statistically based prediction methodologies, accounting for the stochastic nature of SET. An analytical percolation model has been successful in explaining the statistical Weibull distribution of SET time and SET voltage in addition to the power-law voltage-time dependence. Two prediction methodologies using constant voltage stress (CVS) and ramp voltage stress (RVS) are proposed to evaluate the SET speed-disturb properties. The RVS method reduces analysis time and cost and yields equivalent results as the CVS method. Furthermore, the RVS method is used to evaluate the device design space and the current status of RRAM technology to meet the strict requirement of the SET speed-disturb dilemma.