Browsing by Author "Liu, Keng-Ming"

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A Field-Programmable Lab-on-a-Chip with Built-in Self-Test Circuit and Low-Power Sensor-Fusion Solution in 0.35 mu m Standard CMOS Process
(2015)
Lai, Kelvin Yi-Tse
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Shiu, Ming-Feng
;
Lu, Yi-Wen
;
Ho, Yingchieh
;
Kao, Yu-Chi
This paper presents a field programmable lab-on-a-chip (FPLOC) with microfluidics actuation, droplet location/category readback, built-in-self-test (BIST), and bioassays detection. This FPLOC is composed of 1,800 MEDA microelectrodes and integrates a set of microfluidic operations to perform droplet moving/cutting/mixing. Besides, capacitive sensing circuits are considered for system automation, droplets classification, malfunctioning microelectrodes and surface flatness testing, and biomedical detection. Implemented in 0.35 mu m standard CMOS process in 7.4mm(2), the FPLOC demonstrates microfluidic operations under 25V at 1KHz, 1.3fF resolution for droplet location/category/chip BIST maps readback at 1MHz, and 0.34fF sensitivity of capacitive measurement window for biomedical detection at 1KHz.
Analytical Model of Subthreshold Current and Threshold Voltage for Fully Depleted Double-Gated Junctionless Transistor
(2012-02-01)
Lin, Zer-Ming
;
Lin, Horng-Chih
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Liu, Keng-Ming
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
In this study, we derive an analytical model of an electric potential of a double-gated (DG) fully depleted (FD) junctionless (J-less) transistor by solving the two-dimensional Poisson's equation. On the basis of this two-dimensional electric potential model, subthreshold current and swing can be calculated. Threshold voltage roll-off can also be estimated with analytical forms derived using the above model. The calculated results of electric potential, subthreshold current and threshold voltage roll-off are all in good agreement with the results of technology computer aided design (TCAD) simulation. The model proposed in this paper may help in the development of a compact model for simulation program with integrated circuit emphasis (SPICE) simulation and in providing deeper insights into the characteristics of short-channel J-less transistors. (C) 2012 The Japan Society of Applied Physics
Design of a Micro-Electrode Cell for Programmable Lab-on-CMOS Platform
(2016)
Ho, Yingchieh
;
Wang, Gary
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Lai, Kelvin Yi-Tse
;
Lug, Yi-Wen
;
Liu, Keng-Ming
This paper presents a programmable lab-on-CMOS (LoCMOS) with micro-electrode cell array. Array structure is suitable for programmable like CMOS VLSIs. In order to improve the utilization, each micro-electrode cell is composed of actuation and sensing circuit. In addition, a CMOS-compatible extended drain MOSFET (EDMOS) is adopted under a 3V supply. This LoCMOS platform is composed of 1,800 microelectrodes with exploiting EDMOS to enable droplet actuations. Through its field programmability, the chip can successfully perform all microfluidic operations, droplet moving/cutting/mixing on a 2-dimenional microelectrode cell array. Implemented in 0.35um standard CMOS process, the LoCMOS platform demonstrates microfluidic functions and droplet detection. Measured results show successfully for actuation and real-time droplet location sensing.
Investigation of p-type junction-less independent double-gate poly-Si nano-strip transistors
(2014-01-01)
Liu, Keng-Ming
;
Lin, Zer-Ming
;
Wu, Jiun-Peng
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
In this study, novel independent double-gate (IDG) junction-less (J-less) polycrystalline silicon (poly-Si) nano-strip transistors have been fabricated and investigated. Inversion-mode (IM) IDG poly-Si nano-strip transistors with the undoped channel have also been fabricated for comparison. The experimental data show the superior on-state current of J-less transistors over that of IM transistors mainly due to the reduction of the channel resistance (R-ch). However, the drain-induced barrier lowering of the J-less transistors is larger than that of IM transistors but the double-gate (DG) configuration can mitigate this problem to some extent. Besides, the subthreshold swing and its fluctuation of the J-less transistors are worse than those of IM transistors under the single-gate operation. Fortunately, this issue can be significantly improved by the aid of DG configuration according to our experimental results. We also demonstrate the possibility of changing the threshold voltage (V-th) under IDG operation for the J-less IDG nano-strip transistors.
The effects of channel doping concentration for n-type junction-less double-gate poly-Si nanostrip transistors
(2014-05-01)
Liu, Keng-Ming
;
Peng, Fan-I
;
Peng, Kang-Ping
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
In this study, novel n-type double-gate (DG) junction-less (J-less) polycrystalline silicon (poly-Si) nanostrip transistors with different channel doping concentrations (N-C) have been fabricated and investigated. The effects of channel doping concentration on device characteristics were examined comprehensively in this work. The experimental data show that as the channel doping concentration of the J-less device increases, the threshold voltage (V-TH) becomes more negative. Besides, the drain-induced barrier lowering and the subthreshold swing of the J-less transistors become larger as the channel doping increases. We also found that as the channel doping increases, the off-current (I-OFF) increases and the on-current (I-ON) actually decreases due to the doping-dependent mobility degradation. The conduction mechanisms under different channel doping concentrations were also investigated by TCAD simulation. The experimental results suggest that the n-type DG nanostrip J-less transistor with lower channel doping will have superior device characteristics.