Browsing by Author "Liu, Tung-Yu"

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Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
(2015-09-01)
Liu, Tung-Yu
;
Pan, Fu-Ming
;
Sheu, Jeng-Tzong
;
材料科學與工程學系奈米科技碩博班
;
分子醫學與生物工程研究所
A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high I-on/I-off current ratio of 7 x 10(8) (V-G = 4 V and V-D = 1 V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.
Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels
(2015-06-01)
Tso, Chia-Tsung
;
Liu, Tung-Yu
;
Sheu, Jeng-Tzong
;
材料科學與工程學系
;
Department of Materials Science and Engineering
Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 mu m lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; similar to 124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 +/- 13 mV/V), and a high I-ON/I-OFF current ratio (similar to 1 x 10(9)) under a relatively low voltage condition (V-D = 0.3 V, V-G = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area. (C) 2015 The Japan Society of Applied Physics
Gate-All-Around Single-Crystal-Like Poly-Si Nanowire TFTs With a Steep-Subthreshold Slope
(2013-04-01)
Liu, Tung-Yu
;
Lo, Shen-Chuan
;
Sheu, Jeng-Tzong
;
材料科學與工程學系
;
Department of Materials Science and Engineering
We investigate the characteristics of single-crystallike (SCL) poly-Si nanowire (SCL poly-Si NW) thin-film-transistors with gate-all-around (GAA) structures. The GAA SCL poly-Si NWs are prepared by a modified sidewall spacer process utilizing an amorphous silicon (alpha-Si) mesa structure. The combination of the high surface-to-volume ratio of the NW and a nominal gate length of 0.25 mu m lead to clear improvement in electrical performance, including a steep subthreshold swing (90 +/- 15 mV/dec), a virtual absence of drain-induced barrier lowering (21 +/- 13 mV/V), and a very high ON/OFF current ratio similar to 7 x 10(7) (V-D = 1 V, V-G = 3 V).
Temperature- and doping-concentration-dependent characteristics of junctionless gate-all-around polycrystalline-silicon thin-film transistors
(2017-04-01)
Tso, Chia-Tsung
;
Liu, Tung-Yu
;
Pan, Fu-Ming
;
Sheu, Jeng-Tzong
;
材料科學與工程學系
The temperature effects of both gate-all-around polycrystalline silicon nanowire (GAA poly-Si NW) junctionless (JL) and inversion mode (IM) transistor devices at various temperatures (77-410 K) were investigated. The electrical characteristics of these devices, such as subthreshold swing (SS), threshold voltage (Vth), and drain-induced barrier lowering (DIBL), were also characterized and compared in this study. Moreover, JL devices with different doping concentrations at various temperatures were also discussed. Both Vth and I-on showed significant doping concentration dependences for JL devices with doping concentrations of 1 x 10(19) and 5 x 10(19) cm(-3). However, the electrical characteristics of JL devices showed less thermal sensitivity when the doping concentration reached 10(20) cm(-3) . (C) 2017 The Japan Society of Applied Physics