Browsing by Author "Liu, Yao-Chia"

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A 0.1-3GHz Cell-Based Fractional-N All Digital Phase-Locked Loop Using Delta Sigma Noise-Shaped Phase Detector
(2013-01-01)
Liu, Yao-Chia
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Chen, Wei-Zen
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Chou, Mao-Hsuan
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Tsai, Tsung-Hsien
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Lee, Yen-Wei
A 0.1-3 GHz, cell-based, fractional-N ADPLL with Delta Sigma noise-shaped phase detector is presented. By dithering the reference phase and quantization phase error through an additional feedback path, linear phase detection and zero stabilization are accomplished without resort to sophisticated time to digital converter (TDC). The measured rms jitter from a 3GHz carrier is 1.9 ps with a multiplication factor of 60. Implemented in TSMC 40nm general purpose superb CMOS technology, the chip size is 280um x 240um.
A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery
(2015-11-01)
Hong, Zheng-Hao
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Liu, Yao-Chia
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Chen, Wei-Zen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A 19-27 Gbps receiver comprised of a continuous-time linear equalizer (CTLE) followed by a 2-tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broadband PLL to facilitate ISI and jitter suppression over wide-band operation. To accommodate different channel response, an automatic threshold tracking (ATT) circuit combining with sign-sign least mean square (LMS) adaptive engine is realized. A quadrature relaxation-type oscillator is proposed to provide the sampling phases without bulky inductors. It also provides the advantages of small form factor and wide range operation (19-27 Gbps) to compensate 20 dB channel loss at 12.5 GHz. Fabricated in a 40 nm CMOS technology, the whole receiver manifests an energy efficiency of 3.12 pJ/bit at 27 Gbps operation. The core area is 0.09 mm(2) only.