Browsing by Author "Liu, Yi-Sheng"

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Analysis and Solution to Overcome EOS Failure Induced by Latchup Test in A High-Voltage Integrated Circuits
(2013-01-01)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
Liu, Yi-Sheng
;
Chuang, Ming-Nan
;
電子工程學系及電子研究所
Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.
Analysis and Solution to Overcome EOS Failure Induced by Latchup Test in A High-Voltage Integrated Circuits
(2013)
Tsai, Hui-Wen
;
Ker, Ming-Dou
;
Liu, Yi-Sheng
;
Chuang, Ming-Nan
;
電子工程學系及電子研究所
Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.