Browsing by Author "Lo, Wen-Cheng"

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Carrier transportation mechanism of the TaN/HfO(2)/IL/Si structure with silicon surface fluorine implantation
(2008-07-01)
Wu, Woei Cherng
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Lai, Chao-Sung
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Wang, Tzu-Ming
;
Wang, Jer-Chyi
;
Hsu, Chih Wei
In this paper, the current transportation mechanism of HfO(2) gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO(2)/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO(2) barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HIM conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO(2) conduction band, which contributes to Frenkel-Poole conduction.
Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation
(2008)
Wu, Woei-Chemg
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Lai, Chao-Sung
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Lee, Shih-Ching
;
Ma, Ming-Wen
;
Chao, Tien-Sheng
In this paper, we demonstrate TaN/Fluorinated HfO2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively. A physical model of shallow and deep trapping level affected by fluorine was proposed to explain the NBTI and PBTI improvements.
Performance and interface characterization for contact etch stop layer-strained nMOSFET with HfO2 gate dielectrics under pulsed-IV measurement
(2008)
Wu, Woei-Cherng
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Chao, Tien-Sheng
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Chiu, Te-Hsin
;
Wang, Jer-Chyi
;
Lai, Chao-Sung
In this paper, high-performance contact etching stop layer (CESL)-strained n-metal-oxide-semiconductor field effect transistor (nMOSFET) with HfO2 gate dielectrics has been successfully demonstrated. The effects of the CESL layer to the high-k without trapping behaviors are investigated by the pulse current-voltage (IV) technique for the first time. It is found that a roughly 55 and 60% increase of mobility and I-ON, respectively, can be achieved for the 300 nm CESL HfO2 nMOSFET using pulsed-IV measurement. Furthermore, a superior HfO2/Si interface for CESL devices is observed, demonstrated by an obvious interface state density reduction (6 x 10(11)-9 x 10(10) cm(-2)).
Performance enhancement by local strain in (110) channel n-channel metal-oxide-semicondiactor field-effect transistors on (111) substrate
(2007-09-01)
Lo, Wen-Cheng
;
Ku, Ya-Hsin
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Lee, Yao-Jen
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Chao, Tien-Sheng
;
Chang, Chun-Yen
In this study, an n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) fabricated with local strained channel techniques on a (111) Si substrate using a SiN capping layer with high mechanical stress and the stack gate of amorphous silicon (alpha-Si) and polycrystal line silicon (poly-Si) was investigated. By using these techniques, the performance improvement of the nMOSFETs in the (110) channel direction on the (111) substrate was achieved. The on-current and transconductance (G) increased with increasing SiN capping layer or alpha-Si layer thickness. Our experimental results show that devices with a 700 A a-Si layer show a 6.7% on-current improvement percentage relative to those with a 200 A. alpha-Si layer, and a corresponding G. improvement percentage of 10.2%. In addition, charge pumping current/interface state density decreased for the samples with a thicker SiN layer.
Performance enhancement for strained HfO(2) nMOSFET with contact etch stop layer (CESL) under pulsed-IV measurement
(2007)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
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Chiu, Te-Hsin
;
Wang, Jer-Chyi
;
Lai, Chao-Sung
High-performance CESL strained nMOSFET with HfO(2) gate dielectrics has been successfully demonstrated in this work. It is found that, the transconductance (g(m)) and driving current (I(on)) of the nMOSFETs increase 70% and 90%, respectively, of the increase of devices with a 300 nm capping nitride layer. A superior HfO(2)/Si interface for CESL-devices is observed, demonstrated by an obvious interface state density reduction (6.56x10(11) to 9.85x10(10) cm(-2)). Further, a roughly 50% and 60% increase of g(m) and I(on), respectively, can be achieved for the 300 nm SiN-capped HfO(2) nMOSFET without considering charge trapping under pulsed-IV measurement.
Positive Bias Temperature Instability (PBTI) Characteristics of Contact-Etch-Stop-Layer-Induced Local-Tensile-Strained HfO(2) nMOSFET
(2008-12-01)
Wu, Woei-Cherng
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Chao, Tien-Sheng
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Chiu, Te-Hsin
;
Wang, Jer-Chyi
;
Lai, Chao-Sung
The positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer (CESL)-strained HfO(2) nMOSFET are thoroughly investigated. For the first time, the effects of CESL on an HfO(2) dielectric are investigated for PBTI characteristics. A roughly 50% reduction Of V(TH) shift can be achieved for the 300-nm CESL HfO(2) nMOSFET after 1000-s PBTI stressing without obvious HfO(2)/Si interface degradation, as demonstrated by the negligible charge pumping current increase (< 4%). In addition, the HfO(2) film of CESL devices has a deeper trapping level (0.83 eV), indicating that most of the shallow traps (0.75 eV) in as-deposited HfO(2) film can be eliminated for CESL devices.
Positive Bias Temperature Instability (PBTI) Characteristics of Contact-Etch-Stop-Layer-Induced Local-Tensile-Strained HfO2 nMOSFET
(2008-12-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Chiu, Te-Hsin
;
Wang, Jer-Chyi
;
Lai, Chao-Sung
The positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer (CESL)-strained HfO2 nMOSFET are thoroughly investigated. For the first time, the effects of CESL on an HfO2 dielectric are investigated for PBTI characteristics. A roughly 50% reduction Of V-TH shift can be achieved for the 300-nm CESL HfO2 nMOSFET after 1000-s PBTI stressing without obvious HfO2/Si interface degradation, as demonstrated by the negligible charge pumping current increase (< 4%). In addition, the HfO2 film of CESL devices has a deeper trapping level (0.83 eV), indicating that most of the shallow traps (0.75 eV) in as-deposited HfO2 film can be eliminated for CESL devices.
Systematical study of reliability issues in plasma-nitrided and thermally nitrided oxides for advanced dual-gate oxide p-channel metal-oxide-semiconductor field-effect transistors
(2007-03-01)
Lo, Wen-Cheng
;
Wu, Shien-Yang
;
Chang, Sun-Jay
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Chiang, Mu-Chi
;
Lin, Chih-Yung
In this study, we compared the effects of negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) on the core and input/output (I/O) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) fabricated using the different gate dielectrics of plasma nitrided oxide (PNO) and thermally nitrided oxide (TNO). The mobility and constant overdrive current of the PMOSFETs fabricated using PNO as a gate oxide material are about 30 and 23% higher than those of the devices fabricated using TNO, respectively. The core PMOSFETs fabricated using PNO show a better NBTI and HCI immunity than those fabricated using TNO owing to the lower nitrogen concentration at the SiO2/Si-substrate interface. However, the I/O PMOSFETs fabricated using PNO show a higher HCI-induced degradation rate because of a higher oxide bulk trap density but a better NBTI than the devices fabricated using TNO at a normal stressed bias due to a low interface trap density.
Trapping and de-trapping characteristics in PBTI and dynamic PBTI between HfO2 and HfSiON gate dielectrics
(2008)
Lin, We-Liang
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Lee, Yao-Jen
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Lo, Wen-Cheng
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Chen, King-Sheng
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Hou, Y. T.
PBTI degradation for HfO2 and HfSiON NMOSFETs has been demonstrated. The generated oxide trap dominated the PBTI characteristics for Hf-based gate dielectrics. In addition, the reduction of Delta V-TH and oxide trap generation under PBTI indicates that the HfSiON is better than HfO2. On the other hand, the electron trapping/de-trapping effect has been investigated. As compared to HfO2 dielectrics, the HfSiON has shallower charge trapping level due to elimination of deep dielectric vacancies, and the temperature effects are quite different between the HfSiON and HfO2 gate dielectrics.