Browsing by Author "Lu, Ching-Ho"

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Methodology of Generating Dual-Cell-Aware Tests
(2017-01-01)
Huang, Yu-Hao
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Lu, Ching-Ho
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Wu, Tse-Wei
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Nien, Yu-Teng
;
Chen, Ying-Yen
This paper introduces a novel fault model, called the dual-cell-aware (DCA) fault model, which targets the short defects locating between two adjacent standard cells placed in the layout. A layout-based methodology is also presented to automatically extract valid DCA faults from targeted designs and cell libraries. The identified DCA faults are outputted in a format that can be applied to a commercial ATPG tool for test generation. The result of ATPG and fault simulation based on industrial designs have demonstrated that the DCA faults cannot be fully covered by the tests of conventional fault models including stuck-at, transition, bridge and cell-aware faults and hence require their own designated tests to detect.
Testing Methods for a Write-Assist Disturbance-Free Dual-Port SRAM
(2014)
Yang, Hao-Yu
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Lin, Chen-Wei
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Huang, Chao-Ying
;
Lu, Ching-Ho
;
Lai, Chen-An
The recent research works of dual-port SRAM have focused on developing new write-assist techniques to suppress the potential inter-port write disturbance under low operating voltage and high process variation. However, the testing related issues induced by those newly proposed write-assist techniques have not been discussed yet in the previous literatures. In this paper, we first implemented a new write-assist dual-port SRAM proposed in [10] by using a 28nm LP process and then discussed the faulty behavior of injecting different resistive-open defects into both the SRAM cell and write-assist circuit. Next, we developed new test methods to detect the hard-to-detect resistive-open defects and proposed a corresponding March-like algorithm that covers a widely used March C-as well as the proposed test methods. Last, the required DfT for the proposed test methods was also discussed.