Browsing by Author "Lu, HungWen"

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A Scalable Digitalized Buffer for Gigabit I/O
(2008)
Lu, HungWen
;
Su, ChauChin
;
Liu, Chien-Nan
;
交大名義發表
;
National Chiao Tung University
A serial I/O composed of inverters and transmission gates only is proposed to achieve high supply voltage scalability and low area overhead. The inverter with an inductive biasing circuit can extend bandwidth, and reduce the SSN simultaneously. With a TSMC 0.18 mu m CMOS process, the I/O occupies an area of 0.014mm(2) and operates from 4Gbps@1.9V to 1.5Gbps@1.1V.